xref: /openbmc/u-boot/arch/arm/cpu/pxa/start.S (revision 301e8038) 
1/*
2 *  armboot - Startup Code for XScale CPU-core
3 *
4 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
5 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
7 *  Copyright (C) 2001	Alex Zuepke <azu@sysgo.de>
8 *  Copyright (C) 2001	Marius Groger <mag@sysgo.de>
9 *  Copyright (C) 2002	Alex Zupke <azu@sysgo.de>
10 *  Copyright (C) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
12 *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 *  Copyright (C) 2003	Kshitij <kshitij@ti.com>
14 *  Copyright (C) 2003	Richard Woodruff <r-woodruff2@ti.com>
15 *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
16 *  Copyright (C) 2004	Texas Instruments <r-woodruff2@ti.com>
17 *  Copyright (C) 2010	Marek Vasut <marek.vasut@gmail.com>
18 *
19 * See file CREDITS for list of people who contributed to this
20 * project.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
38#include <asm-offsets.h>
39#include <config.h>
40#include <version.h>
41
42#ifdef CONFIG_CPU_PXA25X
43#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
44#error "Init SP address must be set to 0xfffff800 for PXA250"
45#endif
46#endif
47
48.globl _start
49_start: b	reset
50#ifdef CONFIG_SPL_BUILD
51	ldr	pc, _hang
52	ldr	pc, _hang
53	ldr	pc, _hang
54	ldr	pc, _hang
55	ldr	pc, _hang
56	ldr	pc, _hang
57	ldr	pc, _hang
58
59_hang:
60	.word	do_hang
61	.word	0x12345678
62	.word	0x12345678
63	.word	0x12345678
64	.word	0x12345678
65	.word	0x12345678
66	.word	0x12345678
67	.word	0x12345678	/* now 16*4=64 */
68#else
69	ldr	pc, _undefined_instruction
70	ldr	pc, _software_interrupt
71	ldr	pc, _prefetch_abort
72	ldr	pc, _data_abort
73	ldr	pc, _not_used
74	ldr	pc, _irq
75	ldr	pc, _fiq
76
77_undefined_instruction: .word undefined_instruction
78_software_interrupt:	.word software_interrupt
79_prefetch_abort:	.word prefetch_abort
80_data_abort:		.word data_abort
81_not_used:		.word not_used
82_irq:			.word irq
83_fiq:			.word fiq
84_pad:			.word 0x12345678 /* now 16*4=64 */
85#endif	/* CONFIG_SPL_BUILD */
86.global _end_vect
87_end_vect:
88
89	.balignl 16,0xdeadbeef
90/*
91 *************************************************************************
92 *
93 * Startup Code (reset vector)
94 *
95 * do important init only if we don't start from memory!
96 * setup Memory and board specific bits prior to relocation.
97 * relocate armboot to ram
98 * setup stack
99 *
100 *************************************************************************
101 */
102
103.globl _TEXT_BASE
104_TEXT_BASE:
105#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
106	.word	CONFIG_SPL_TEXT_BASE
107#else
108	.word	CONFIG_SYS_TEXT_BASE
109#endif
110
111/*
112 * These are defined in the board-specific linker script.
113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
115 * them null.
116 */
117.globl _bss_start_ofs
118_bss_start_ofs:
119	.word __bss_start - _start
120
121.globl _bss_end_ofs
122_bss_end_ofs:
123	.word __bss_end - _start
124
125.globl _end_ofs
126_end_ofs:
127	.word _end - _start
128
129#ifdef CONFIG_USE_IRQ
130/* IRQ stack memory (calculated at run-time) */
131.globl IRQ_STACK_START
132IRQ_STACK_START:
133	.word	0x0badc0de
134
135/* IRQ stack memory (calculated at run-time) */
136.globl FIQ_STACK_START
137FIQ_STACK_START:
138	.word 0x0badc0de
139#endif
140
141/* IRQ stack memory (calculated at run-time) + 8 bytes */
142.globl IRQ_STACK_START_IN
143IRQ_STACK_START_IN:
144	.word	0x0badc0de
145
146/*
147 * the actual reset code
148 */
149
150reset:
151	/*
152	 * set the cpu to SVC32 mode
153	 */
154	mrs	r0,cpsr
155	bic	r0,r0,#0x1f
156	orr	r0,r0,#0xd3
157	msr	cpsr,r0
158
159#ifndef CONFIG_SKIP_LOWLEVEL_INIT
160	bl  cpu_init_crit
161#endif
162
163#ifdef	CONFIG_CPU_PXA25X
164	bl	lock_cache_for_stack
165#endif
166
167	bl	_main
168
169/*------------------------------------------------------------------------------*/
170
171	.globl	c_runtime_cpu_setup
172c_runtime_cpu_setup:
173
174#ifdef CONFIG_CPU_PXA25X
175	/*
176	 * Unlock (actually, disable) the cache now that board_init_f
177	 * is done. We could do this earlier but we would need to add
178	 * a new C runtime hook, whereas c_runtime_cpu_setup already
179	 * exists.
180	 * As this routine is just a call to cpu_init_crit, let us
181	 * tail-optimize and do a simple branch here.
182	 */
183	b	cpu_init_crit
184#else
185	bx	lr
186#endif
187
188/*
189 *************************************************************************
190 *
191 * CPU_init_critical registers
192 *
193 * setup important registers
194 * setup memory timing
195 *
196 *************************************************************************
197 */
198#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
199cpu_init_crit:
200	/*
201	 * flush v4 I/D caches
202	 */
203	mov	r0, #0
204	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
205	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
206
207	/*
208	 * disable MMU stuff and caches
209	 */
210	mrc	p15, 0, r0, c1, c0, 0
211	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
212	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
213	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
214	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
215	mcr	p15, 0, r0, c1, c0, 0
216
217	mov	pc, lr		/* back to my caller */
218#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
219
220#ifndef CONFIG_SPL_BUILD
221/*
222 *************************************************************************
223 *
224 * Interrupt handling
225 *
226 *************************************************************************
227 */
228@
229@ IRQ stack frame.
230@
231#define S_FRAME_SIZE	72
232
233#define S_OLD_R0	68
234#define S_PSR		64
235#define S_PC		60
236#define S_LR		56
237#define S_SP		52
238
239#define S_IP		48
240#define S_FP		44
241#define S_R10		40
242#define S_R9		36
243#define S_R8		32
244#define S_R7		28
245#define S_R6		24
246#define S_R5		20
247#define S_R4		16
248#define S_R3		12
249#define S_R2		8
250#define S_R1		4
251#define S_R0		0
252
253#define MODE_SVC 0x13
254#define I_BIT	 0x80
255
256/*
257 * use bad_save_user_regs for abort/prefetch/undef/swi ...
258 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
259 */
260
261	.macro	bad_save_user_regs
262	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
263	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
264
265	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
266	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
267	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
268
269	add	r5, sp, #S_SP
270	mov	r1, lr
271	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
272	mov	r0, sp				@ save current stack into r0 (param register)
273	.endm
274
275	.macro	irq_save_user_regs
276	sub	sp, sp, #S_FRAME_SIZE
277	stmia	sp, {r0 - r12}			@ Calling r0-r12
278	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
279	stmdb	r8, {sp, lr}^			@ Calling SP, LR
280	str	lr, [r8, #0]			@ Save calling PC
281	mrs	r6, spsr
282	str	r6, [r8, #4]			@ Save CPSR
283	str	r0, [r8, #8]			@ Save OLD_R0
284	mov	r0, sp
285	.endm
286
287	.macro	irq_restore_user_regs
288	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
289	mov	r0, r0
290	ldr	lr, [sp, #S_PC]			@ Get PC
291	add	sp, sp, #S_FRAME_SIZE
292	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
293	.endm
294
295	.macro get_bad_stack
296	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
297
298	str	lr, [r13]			@ save caller lr in position 0 of saved stack
299	mrs	lr, spsr			@ get the spsr
300	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
301
302	mov	r13, #MODE_SVC			@ prepare SVC-Mode
303	@ msr	spsr_c, r13
304	msr	spsr, r13			@ switch modes, make sure moves will execute
305	mov	lr, pc				@ capture return pc
306	movs	pc, lr				@ jump to next instruction & switch modes.
307	.endm
308
309	.macro get_bad_stack_swi
310	sub	r13, r13, #4			@ space on current stack for scratch reg.
311	str	r0, [r13]			@ save R0's value.
312	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
313	str	lr, [r0]			@ save caller lr in position 0 of saved stack
314	mrs	lr, spsr			@ get the spsr
315	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
316	ldr	lr, [r0]			@ restore lr
317	ldr	r0, [r13]			@ restore r0
318	add	r13, r13, #4			@ pop stack entry
319	.endm
320
321	.macro get_irq_stack			@ setup IRQ stack
322	ldr	sp, IRQ_STACK_START
323	.endm
324
325	.macro get_fiq_stack			@ setup FIQ stack
326	ldr	sp, FIQ_STACK_START
327	.endm
328#endif	/* CONFIG_SPL_BUILD */
329
330/*
331 * exception handlers
332 */
333#ifdef CONFIG_SPL_BUILD
334	.align	5
335do_hang:
336	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
337	bl	hang				/* hang and never return */
338#else	/* !CONFIG_SPL_BUILD */
339	.align	5
340undefined_instruction:
341	get_bad_stack
342	bad_save_user_regs
343	bl	do_undefined_instruction
344
345	.align	5
346software_interrupt:
347	get_bad_stack_swi
348	bad_save_user_regs
349	bl	do_software_interrupt
350
351	.align	5
352prefetch_abort:
353	get_bad_stack
354	bad_save_user_regs
355	bl	do_prefetch_abort
356
357	.align	5
358data_abort:
359	get_bad_stack
360	bad_save_user_regs
361	bl	do_data_abort
362
363	.align	5
364not_used:
365	get_bad_stack
366	bad_save_user_regs
367	bl	do_not_used
368
369#ifdef CONFIG_USE_IRQ
370
371	.align	5
372irq:
373	get_irq_stack
374	irq_save_user_regs
375	bl	do_irq
376	irq_restore_user_regs
377
378	.align	5
379fiq:
380	get_fiq_stack
381	/* someone ought to write a more effiction fiq_save_user_regs */
382	irq_save_user_regs
383	bl	do_fiq
384	irq_restore_user_regs
385
386#else
387
388	.align	5
389irq:
390	get_bad_stack
391	bad_save_user_regs
392	bl	do_irq
393
394	.align	5
395fiq:
396	get_bad_stack
397	bad_save_user_regs
398	bl	do_fiq
399
400#endif
401	.align 5
402#endif	/* CONFIG_SPL_BUILD */
403
404
405/*
406 * Enable MMU to use DCache as DRAM.
407 *
408 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
409 * other possible memory available to hold stack.
410 */
411#ifdef CONFIG_CPU_PXA25X
412.macro CPWAIT reg
413	mrc	p15, 0, \reg, c2, c0, 0
414	mov	\reg, \reg
415	sub	pc, pc, #4
416.endm
417lock_cache_for_stack:
418	/* Domain access -- enable for all CPs */
419	ldr	r0, =0x0000ffff
420	mcr	p15, 0, r0, c3, c0, 0
421
422	/* Point TTBR to MMU table */
423	ldr	r0, =mmutable
424	mcr	p15, 0, r0, c2, c0, 0
425
426	/* Kick in MMU, ICache, DCache, BTB */
427	mrc	p15, 0, r0, c1, c0, 0
428	bic	r0, #0x1b00
429	bic	r0, #0x0087
430	orr	r0, #0x1800
431	orr	r0, #0x0005
432	mcr	p15, 0, r0, c1, c0, 0
433	CPWAIT	r0
434
435	/* Unlock Icache, Dcache */
436	mcr	p15, 0, r0, c9, c1, 1
437	mcr	p15, 0, r0, c9, c2, 1
438
439	/* Flush Icache, Dcache, BTB */
440	mcr	p15, 0, r0, c7, c7, 0
441
442	/* Unlock I-TLB, D-TLB */
443	mcr	p15, 0, r0, c10, c4, 1
444	mcr	p15, 0, r0, c10, c8, 1
445
446	/* Flush TLB */
447	mcr	p15, 0, r0, c8, c7, 0
448
449	/* Allocate 4096 bytes of Dcache as RAM */
450
451	/* Drain pending loads and stores */
452	mcr	p15, 0, r0, c7, c10, 4
453
454	mov	r4, #0x00
455	mov	r5, #0x00
456	mov	r2, #0x01
457	mcr	p15, 0, r0, c9, c2, 0
458	CPWAIT	r0
459
460	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
461	mov	r0, #128
462	ldr	r1, =0xfffff000
463
464alloc:
465	mcr	p15, 0, r1, c7, c2, 5
466	/* Drain pending loads and stores */
467	mcr	p15, 0, r0, c7, c10, 4
468	strd	r4, [r1], #8
469	strd	r4, [r1], #8
470	strd	r4, [r1], #8
471	strd	r4, [r1], #8
472	subs	r0, #0x01
473	bne	alloc
474	/* Drain pending loads and stores */
475	mcr	p15, 0, r0, c7, c10, 4
476	mov	r2, #0x00
477	mcr	p15, 0, r2, c9, c2, 0
478	CPWAIT	r0
479
480	mov	pc, lr
481
482.section .mmutable, "a"
483mmutable:
484	.align	14
485	/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
486	.set	__base, 0
487	.rept	0xfff
488	.word	(__base << 20) | 0xc12
489	.set	__base, __base + 1
490	.endr
491
492	/* 0xfff00000 : 1:1, cached mapping */
493	.word	(0xfff << 20) | 0x1c1e
494#endif	/* CONFIG_CPU_PXA25X */
495