184ad6884SPeter Tyser/* 220f7b1b7SMarek Vasut * armboot - Startup Code for XScale CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 584ad6884SPeter Tyser * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 684ad6884SPeter Tyser * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 784ad6884SPeter Tyser * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 820f7b1b7SMarek Vasut * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 920f7b1b7SMarek Vasut * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 1020f7b1b7SMarek Vasut * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 1284ad6884SPeter Tyser * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 1320f7b1b7SMarek Vasut * Copyright (C) 2003 Kshitij <kshitij@ti.com> 1420f7b1b7SMarek Vasut * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 1520f7b1b7SMarek Vasut * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 1620f7b1b7SMarek Vasut * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 1720f7b1b7SMarek Vasut * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 1884ad6884SPeter Tyser * 191a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 2084ad6884SPeter Tyser */ 2184ad6884SPeter Tyser 2225ddd1fbSWolfgang Denk#include <asm-offsets.h> 2384ad6884SPeter Tyser#include <config.h> 247f4cfcf4SMarek Vasut 2584ad6884SPeter Tyser/* 2620f7b1b7SMarek Vasut ************************************************************************* 2720f7b1b7SMarek Vasut * 2884ad6884SPeter Tyser * Startup Code (reset vector) 2984ad6884SPeter Tyser * 3020f7b1b7SMarek Vasut * do important init only if we don't start from memory! 3120f7b1b7SMarek Vasut * setup Memory and board specific bits prior to relocation. 3220f7b1b7SMarek Vasut * relocate armboot to ram 3320f7b1b7SMarek Vasut * setup stack 3420f7b1b7SMarek Vasut * 3520f7b1b7SMarek Vasut ************************************************************************* 3684ad6884SPeter Tyser */ 3784ad6884SPeter Tyser 3841623c91SAlbert ARIBAUD .globl reset 395347f68cSHeiko Schocher 405347f68cSHeiko Schocherreset: 415347f68cSHeiko Schocher /* 425347f68cSHeiko Schocher * set the cpu to SVC32 mode 435347f68cSHeiko Schocher */ 445347f68cSHeiko Schocher mrs r0,cpsr 455347f68cSHeiko Schocher bic r0,r0,#0x1f 465347f68cSHeiko Schocher orr r0,r0,#0xd3 475347f68cSHeiko Schocher msr cpsr,r0 485347f68cSHeiko Schocher 4920f7b1b7SMarek Vasut#ifndef CONFIG_SKIP_LOWLEVEL_INIT 5020f7b1b7SMarek Vasut bl cpu_init_crit 5120f7b1b7SMarek Vasut#endif 525347f68cSHeiko Schocher 53abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 547f4cfcf4SMarek Vasut bl lock_cache_for_stack 557f4cfcf4SMarek Vasut#endif 567f4cfcf4SMarek Vasut 57e05e5de7SAlbert ARIBAUD bl _main 585347f68cSHeiko Schocher 595347f68cSHeiko Schocher/*------------------------------------------------------------------------------*/ 60e05e5de7SAlbert ARIBAUD 61e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 62e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 63e05e5de7SAlbert ARIBAUD 643da0e575SAlbert ARIBAUD#ifdef CONFIG_CPU_PXA25X 653da0e575SAlbert ARIBAUD /* 663da0e575SAlbert ARIBAUD * Unlock (actually, disable) the cache now that board_init_f 673da0e575SAlbert ARIBAUD * is done. We could do this earlier but we would need to add 683da0e575SAlbert ARIBAUD * a new C runtime hook, whereas c_runtime_cpu_setup already 693da0e575SAlbert ARIBAUD * exists. 703da0e575SAlbert ARIBAUD * As this routine is just a call to cpu_init_crit, let us 713da0e575SAlbert ARIBAUD * tail-optimize and do a simple branch here. 723da0e575SAlbert ARIBAUD */ 733da0e575SAlbert ARIBAUD b cpu_init_crit 743da0e575SAlbert ARIBAUD#else 75e05e5de7SAlbert ARIBAUD bx lr 763da0e575SAlbert ARIBAUD#endif 77e05e5de7SAlbert ARIBAUD 7820f7b1b7SMarek Vasut/* 7920f7b1b7SMarek Vasut ************************************************************************* 8020f7b1b7SMarek Vasut * 8120f7b1b7SMarek Vasut * CPU_init_critical registers 8220f7b1b7SMarek Vasut * 8320f7b1b7SMarek Vasut * setup important registers 8420f7b1b7SMarek Vasut * setup memory timing 8520f7b1b7SMarek Vasut * 8620f7b1b7SMarek Vasut ************************************************************************* 8720f7b1b7SMarek Vasut */ 88abc20abaSMarek Vasut#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 8920f7b1b7SMarek Vasutcpu_init_crit: 9020f7b1b7SMarek Vasut /* 9120f7b1b7SMarek Vasut * flush v4 I/D caches 9220f7b1b7SMarek Vasut */ 9320f7b1b7SMarek Vasut mov r0, #0 9420f7b1b7SMarek Vasut mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 9520f7b1b7SMarek Vasut mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 962cad92fdSMarek Vasut 9720f7b1b7SMarek Vasut /* 9820f7b1b7SMarek Vasut * disable MMU stuff and caches 9920f7b1b7SMarek Vasut */ 10020f7b1b7SMarek Vasut mrc p15, 0, r0, c1, c0, 0 101097d86d0SMike Dunn bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 10220f7b1b7SMarek Vasut bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 103*ba10b852SYuichiro Goto orr r0, r0, #0x00000002 @ set bit 1 (A) Align 10420f7b1b7SMarek Vasut mcr p15, 0, r0, c1, c0, 0 10584ad6884SPeter Tyser 10620f7b1b7SMarek Vasut mov pc, lr /* back to my caller */ 107abc20abaSMarek Vasut#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 10884ad6884SPeter Tyser 1097f4cfcf4SMarek Vasut/* 1107f4cfcf4SMarek Vasut * Enable MMU to use DCache as DRAM. 1117f4cfcf4SMarek Vasut * 1127f4cfcf4SMarek Vasut * This is useful on PXA25x and PXA26x in early bootstages, where there is no 1137f4cfcf4SMarek Vasut * other possible memory available to hold stack. 1147f4cfcf4SMarek Vasut */ 115abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 1167f4cfcf4SMarek Vasut.macro CPWAIT reg 1177f4cfcf4SMarek Vasut mrc p15, 0, \reg, c2, c0, 0 1187f4cfcf4SMarek Vasut mov \reg, \reg 1197f4cfcf4SMarek Vasut sub pc, pc, #4 1207f4cfcf4SMarek Vasut.endm 1217f4cfcf4SMarek Vasutlock_cache_for_stack: 1227f4cfcf4SMarek Vasut /* Domain access -- enable for all CPs */ 1237f4cfcf4SMarek Vasut ldr r0, =0x0000ffff 1247f4cfcf4SMarek Vasut mcr p15, 0, r0, c3, c0, 0 1257f4cfcf4SMarek Vasut 1267f4cfcf4SMarek Vasut /* Point TTBR to MMU table */ 1277f4cfcf4SMarek Vasut ldr r0, =mmutable 1287f4cfcf4SMarek Vasut mcr p15, 0, r0, c2, c0, 0 1297f4cfcf4SMarek Vasut 1307f4cfcf4SMarek Vasut /* Kick in MMU, ICache, DCache, BTB */ 1317f4cfcf4SMarek Vasut mrc p15, 0, r0, c1, c0, 0 1327f4cfcf4SMarek Vasut bic r0, #0x1b00 1337f4cfcf4SMarek Vasut bic r0, #0x0087 1347f4cfcf4SMarek Vasut orr r0, #0x1800 1357f4cfcf4SMarek Vasut orr r0, #0x0005 1367f4cfcf4SMarek Vasut mcr p15, 0, r0, c1, c0, 0 1377f4cfcf4SMarek Vasut CPWAIT r0 1387f4cfcf4SMarek Vasut 1397f4cfcf4SMarek Vasut /* Unlock Icache, Dcache */ 1407f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c1, 1 1417f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 1 1427f4cfcf4SMarek Vasut 1437f4cfcf4SMarek Vasut /* Flush Icache, Dcache, BTB */ 1447f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c7, 0 1457f4cfcf4SMarek Vasut 1467f4cfcf4SMarek Vasut /* Unlock I-TLB, D-TLB */ 1477f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c4, 1 1487f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c8, 1 1497f4cfcf4SMarek Vasut 1507f4cfcf4SMarek Vasut /* Flush TLB */ 1517f4cfcf4SMarek Vasut mcr p15, 0, r0, c8, c7, 0 1527f4cfcf4SMarek Vasut 1537f4cfcf4SMarek Vasut /* Allocate 4096 bytes of Dcache as RAM */ 1547f4cfcf4SMarek Vasut 1557f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 1567f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 1577f4cfcf4SMarek Vasut 1587f4cfcf4SMarek Vasut mov r4, #0x00 1597f4cfcf4SMarek Vasut mov r5, #0x00 1607f4cfcf4SMarek Vasut mov r2, #0x01 1617f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 0 1627f4cfcf4SMarek Vasut CPWAIT r0 1637f4cfcf4SMarek Vasut 1647f4cfcf4SMarek Vasut /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 1657f4cfcf4SMarek Vasut mov r0, #128 1667f4cfcf4SMarek Vasut ldr r1, =0xfffff000 1677f4cfcf4SMarek Vasut 1687f4cfcf4SMarek Vasutalloc: 1697f4cfcf4SMarek Vasut mcr p15, 0, r1, c7, c2, 5 1707f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 1717f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 1727f4cfcf4SMarek Vasut strd r4, [r1], #8 1737f4cfcf4SMarek Vasut strd r4, [r1], #8 1747f4cfcf4SMarek Vasut strd r4, [r1], #8 1757f4cfcf4SMarek Vasut strd r4, [r1], #8 1767f4cfcf4SMarek Vasut subs r0, #0x01 1777f4cfcf4SMarek Vasut bne alloc 1787f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 1797f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 1807f4cfcf4SMarek Vasut mov r2, #0x00 1817f4cfcf4SMarek Vasut mcr p15, 0, r2, c9, c2, 0 1827f4cfcf4SMarek Vasut CPWAIT r0 1837f4cfcf4SMarek Vasut 1847f4cfcf4SMarek Vasut mov pc, lr 1857f4cfcf4SMarek Vasut 1867f4cfcf4SMarek Vasut.section .mmutable, "a" 1877f4cfcf4SMarek Vasutmmutable: 1887f4cfcf4SMarek Vasut .align 14 1897f4cfcf4SMarek Vasut /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 1907f4cfcf4SMarek Vasut .set __base, 0 1917f4cfcf4SMarek Vasut .rept 0xfff 1927f4cfcf4SMarek Vasut .word (__base << 20) | 0xc12 1937f4cfcf4SMarek Vasut .set __base, __base + 1 1947f4cfcf4SMarek Vasut .endr 1957f4cfcf4SMarek Vasut 1967f4cfcf4SMarek Vasut /* 0xfff00000 : 1:1, cached mapping */ 1977f4cfcf4SMarek Vasut .word (0xfff << 20) | 0x1c1e 198abc20abaSMarek Vasut#endif /* CONFIG_CPU_PXA25X */ 199