184ad6884SPeter Tyser/* 220f7b1b7SMarek Vasut * armboot - Startup Code for XScale CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 584ad6884SPeter Tyser * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 684ad6884SPeter Tyser * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 784ad6884SPeter Tyser * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 820f7b1b7SMarek Vasut * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 920f7b1b7SMarek Vasut * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 1020f7b1b7SMarek Vasut * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 1284ad6884SPeter Tyser * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 1320f7b1b7SMarek Vasut * Copyright (C) 2003 Kshitij <kshitij@ti.com> 1420f7b1b7SMarek Vasut * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 1520f7b1b7SMarek Vasut * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 1620f7b1b7SMarek Vasut * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 1720f7b1b7SMarek Vasut * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 1884ad6884SPeter Tyser * 1984ad6884SPeter Tyser * See file CREDITS for list of people who contributed to this 2084ad6884SPeter Tyser * project. 2184ad6884SPeter Tyser * 2284ad6884SPeter Tyser * This program is free software; you can redistribute it and/or 2384ad6884SPeter Tyser * modify it under the terms of the GNU General Public License as 2484ad6884SPeter Tyser * published by the Free Software Foundation; either version 2 of 2584ad6884SPeter Tyser * the License, or (at your option) any later version. 2684ad6884SPeter Tyser * 2784ad6884SPeter Tyser * This program is distributed in the hope that it will be useful, 2884ad6884SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 2984ad6884SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 3084ad6884SPeter Tyser * GNU General Public License for more details. 3184ad6884SPeter Tyser * 3284ad6884SPeter Tyser * You should have received a copy of the GNU General Public License 3384ad6884SPeter Tyser * along with this program; if not, write to the Free Software 3484ad6884SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3584ad6884SPeter Tyser * MA 02111-1307 USA 3684ad6884SPeter Tyser */ 3784ad6884SPeter Tyser 3825ddd1fbSWolfgang Denk#include <asm-offsets.h> 3984ad6884SPeter Tyser#include <config.h> 4084ad6884SPeter Tyser#include <version.h> 41*7f4cfcf4SMarek Vasut 42*7f4cfcf4SMarek Vasut#ifdef CONFIG_PXA25X 43*7f4cfcf4SMarek Vasut#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 44*7f4cfcf4SMarek Vasut#error "Init SP address must be set to 0xfffff800 for PXA250" 45*7f4cfcf4SMarek Vasut#endif 46*7f4cfcf4SMarek Vasut#endif 47*7f4cfcf4SMarek Vasut 4884ad6884SPeter Tyser.globl _start 4984ad6884SPeter Tyser_start: b reset 50401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 515ab877b6SMarek Vasut ldr pc, _hang 525ab877b6SMarek Vasut ldr pc, _hang 535ab877b6SMarek Vasut ldr pc, _hang 545ab877b6SMarek Vasut ldr pc, _hang 555ab877b6SMarek Vasut ldr pc, _hang 565ab877b6SMarek Vasut ldr pc, _hang 575ab877b6SMarek Vasut ldr pc, _hang 585ab877b6SMarek Vasut 595ab877b6SMarek Vasut_hang: 605ab877b6SMarek Vasut .word do_hang 615ab877b6SMarek Vasut .word 0x12345678 625ab877b6SMarek Vasut .word 0x12345678 635ab877b6SMarek Vasut .word 0x12345678 645ab877b6SMarek Vasut .word 0x12345678 655ab877b6SMarek Vasut .word 0x12345678 665ab877b6SMarek Vasut .word 0x12345678 675ab877b6SMarek Vasut .word 0x12345678 /* now 16*4=64 */ 685ab877b6SMarek Vasut#else 6984ad6884SPeter Tyser ldr pc, _undefined_instruction 7084ad6884SPeter Tyser ldr pc, _software_interrupt 7184ad6884SPeter Tyser ldr pc, _prefetch_abort 7284ad6884SPeter Tyser ldr pc, _data_abort 7384ad6884SPeter Tyser ldr pc, _not_used 7484ad6884SPeter Tyser ldr pc, _irq 7584ad6884SPeter Tyser ldr pc, _fiq 7684ad6884SPeter Tyser 7784ad6884SPeter Tyser_undefined_instruction: .word undefined_instruction 7884ad6884SPeter Tyser_software_interrupt: .word software_interrupt 7984ad6884SPeter Tyser_prefetch_abort: .word prefetch_abort 8084ad6884SPeter Tyser_data_abort: .word data_abort 8184ad6884SPeter Tyser_not_used: .word not_used 8284ad6884SPeter Tyser_irq: .word irq 8384ad6884SPeter Tyser_fiq: .word fiq 8420f7b1b7SMarek Vasut_pad: .word 0x12345678 /* now 16*4=64 */ 85401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 8620f7b1b7SMarek Vasut.global _end_vect 8720f7b1b7SMarek Vasut_end_vect: 8884ad6884SPeter Tyser 8984ad6884SPeter Tyser .balignl 16,0xdeadbeef 9084ad6884SPeter Tyser/* 9120f7b1b7SMarek Vasut ************************************************************************* 9220f7b1b7SMarek Vasut * 9384ad6884SPeter Tyser * Startup Code (reset vector) 9484ad6884SPeter Tyser * 9520f7b1b7SMarek Vasut * do important init only if we don't start from memory! 9620f7b1b7SMarek Vasut * setup Memory and board specific bits prior to relocation. 9720f7b1b7SMarek Vasut * relocate armboot to ram 9820f7b1b7SMarek Vasut * setup stack 9920f7b1b7SMarek Vasut * 10020f7b1b7SMarek Vasut ************************************************************************* 10184ad6884SPeter Tyser */ 10284ad6884SPeter Tyser 1035347f68cSHeiko Schocher.globl _TEXT_BASE 10484ad6884SPeter Tyser_TEXT_BASE: 10520f7b1b7SMarek Vasut#ifdef CONFIG_SPL_BUILD 10620f7b1b7SMarek Vasut .word CONFIG_SPL_TEXT_BASE 10720f7b1b7SMarek Vasut#else 10814d0a02aSWolfgang Denk .word CONFIG_SYS_TEXT_BASE 10920f7b1b7SMarek Vasut#endif 11084ad6884SPeter Tyser 11184ad6884SPeter Tyser/* 11284ad6884SPeter Tyser * These are defined in the board-specific linker script. 11320f7b1b7SMarek Vasut * Subtracting _start from them lets the linker put their 11420f7b1b7SMarek Vasut * relative position in the executable instead of leaving 11520f7b1b7SMarek Vasut * them null. 11684ad6884SPeter Tyser */ 1176e96cf9aSMarek Vasut.globl _bss_start_ofs 1186e96cf9aSMarek Vasut_bss_start_ofs: 1196e96cf9aSMarek Vasut .word __bss_start - _start 12084ad6884SPeter Tyser 1216e96cf9aSMarek Vasut.globl _bss_end_ofs 1226e96cf9aSMarek Vasut_bss_end_ofs: 12344c6e659SPo-Yu Chuang .word __bss_end__ - _start 12484ad6884SPeter Tyser 125f326cbbaSPo-Yu Chuang.globl _end_ofs 126f326cbbaSPo-Yu Chuang_end_ofs: 127f326cbbaSPo-Yu Chuang .word _end - _start 128f326cbbaSPo-Yu Chuang 12984ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 13084ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 13184ad6884SPeter Tyser.globl IRQ_STACK_START 13284ad6884SPeter TyserIRQ_STACK_START: 13384ad6884SPeter Tyser .word 0x0badc0de 13484ad6884SPeter Tyser 13584ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 13684ad6884SPeter Tyser.globl FIQ_STACK_START 13784ad6884SPeter TyserFIQ_STACK_START: 13884ad6884SPeter Tyser .word 0x0badc0de 13920f7b1b7SMarek Vasut#endif 14084ad6884SPeter Tyser 1415347f68cSHeiko Schocher/* IRQ stack memory (calculated at run-time) + 8 bytes */ 1425347f68cSHeiko Schocher.globl IRQ_STACK_START_IN 1435347f68cSHeiko SchocherIRQ_STACK_START_IN: 1445347f68cSHeiko Schocher .word 0x0badc0de 1455347f68cSHeiko Schocher 1465347f68cSHeiko Schocher/* 1475347f68cSHeiko Schocher * the actual reset code 1485347f68cSHeiko Schocher */ 1495347f68cSHeiko Schocher 1505347f68cSHeiko Schocherreset: 1515347f68cSHeiko Schocher /* 1525347f68cSHeiko Schocher * set the cpu to SVC32 mode 1535347f68cSHeiko Schocher */ 1545347f68cSHeiko Schocher mrs r0,cpsr 1555347f68cSHeiko Schocher bic r0,r0,#0x1f 1565347f68cSHeiko Schocher orr r0,r0,#0xd3 1575347f68cSHeiko Schocher msr cpsr,r0 1585347f68cSHeiko Schocher 15920f7b1b7SMarek Vasut#ifndef CONFIG_SKIP_LOWLEVEL_INIT 16020f7b1b7SMarek Vasut bl cpu_init_crit 16120f7b1b7SMarek Vasut#endif 1625347f68cSHeiko Schocher 163*7f4cfcf4SMarek Vasut#ifdef CONFIG_PXA250 164*7f4cfcf4SMarek Vasut bl lock_cache_for_stack 165*7f4cfcf4SMarek Vasut#endif 166*7f4cfcf4SMarek Vasut 1675347f68cSHeiko Schocher/* Set stackpointer in internal RAM to call board_init_f */ 1685347f68cSHeiko Schochercall_board_init_f: 1695347f68cSHeiko Schocher ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 170296cae73SHeiko Schocher bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 1715347f68cSHeiko Schocher ldr r0, =0x00000000 1725347f68cSHeiko Schocher bl board_init_f 1735347f68cSHeiko Schocher 1745347f68cSHeiko Schocher/*------------------------------------------------------------------------------*/ 17520f7b1b7SMarek Vasut#ifndef CONFIG_SPL_BUILD 1765347f68cSHeiko Schocher/* 1775347f68cSHeiko Schocher * void relocate_code (addr_sp, gd, addr_moni) 1785347f68cSHeiko Schocher * 1795347f68cSHeiko Schocher * This "function" does not return, instead it continues in RAM 1805347f68cSHeiko Schocher * after relocating the monitor code. 1815347f68cSHeiko Schocher * 1825347f68cSHeiko Schocher */ 1835347f68cSHeiko Schocher .globl relocate_code 1845347f68cSHeiko Schocherrelocate_code: 1855347f68cSHeiko Schocher mov r4, r0 /* save addr_sp */ 1865347f68cSHeiko Schocher mov r5, r1 /* save addr of gd */ 1875347f68cSHeiko Schocher mov r6, r2 /* save addr of destination */ 1885347f68cSHeiko Schocher 1895347f68cSHeiko Schocher /* Set up the stack */ 1905347f68cSHeiko Schocherstack_setup: 1915347f68cSHeiko Schocher mov sp, r4 1925347f68cSHeiko Schocher 193*7f4cfcf4SMarek Vasut/* Disable the Dcache RAM lock for stack now */ 194*7f4cfcf4SMarek Vasut#ifdef CONFIG_PXA250 195*7f4cfcf4SMarek Vasut bl cpu_init_crit 196*7f4cfcf4SMarek Vasut#endif 197*7f4cfcf4SMarek Vasut 1985347f68cSHeiko Schocher adr r0, _start 199a1a47d3cSAndreas Bießmann cmp r0, r6 200a1a47d3cSAndreas Bießmann beq clear_bss /* skip relocation */ 201a78fb68fSAndreas Bießmann mov r1, r6 /* r1 <- scratch for copy_loop */ 2026e96cf9aSMarek Vasut ldr r3, _bss_start_ofs 2036e96cf9aSMarek Vasut add r2, r0, r3 /* r2 <- source end address */ 2045347f68cSHeiko Schocher 2055347f68cSHeiko Schochercopy_loop: 20620f7b1b7SMarek Vasut ldmia r0!, {r9-r10} /* copy from source address [r0] */ 20720f7b1b7SMarek Vasut stmia r1!, {r9-r10} /* copy to target address [r1] */ 208da90d4ceSAlbert Aribaud cmp r0, r2 /* until source end address [r2] */ 209da90d4ceSAlbert Aribaud blo copy_loop 2105347f68cSHeiko Schocher 211401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 2126e96cf9aSMarek Vasut /* 2136e96cf9aSMarek Vasut * fix .rel.dyn relocations 2146e96cf9aSMarek Vasut */ 2156e96cf9aSMarek Vasut ldr r0, _TEXT_BASE /* r0 <- Text base */ 216a78fb68fSAndreas Bießmann sub r9, r6, r0 /* r9 <- relocation offset */ 2176e96cf9aSMarek Vasut ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 2186e96cf9aSMarek Vasut add r10, r10, r0 /* r10 <- sym table in FLASH */ 2196e96cf9aSMarek Vasut ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 2206e96cf9aSMarek Vasut add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 2216e96cf9aSMarek Vasut ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 2226e96cf9aSMarek Vasut add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 2235347f68cSHeiko Schocherfixloop: 2246e96cf9aSMarek Vasut ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 22520f7b1b7SMarek Vasut add r0, r0, r9 /* r0 <- location to fix up in RAM */ 2266e96cf9aSMarek Vasut ldr r1, [r2, #4] 2271f52d89fSAndreas Bießmann and r7, r1, #0xff 2281f52d89fSAndreas Bießmann cmp r7, #23 /* relative fixup? */ 2296e96cf9aSMarek Vasut beq fixrel 2301f52d89fSAndreas Bießmann cmp r7, #2 /* absolute fixup? */ 2316e96cf9aSMarek Vasut beq fixabs 2326e96cf9aSMarek Vasut /* ignore unknown type of fixup */ 2336e96cf9aSMarek Vasut b fixnext 2346e96cf9aSMarek Vasutfixabs: 2356e96cf9aSMarek Vasut /* absolute fix: set location to (offset) symbol value */ 2366e96cf9aSMarek Vasut mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 2376e96cf9aSMarek Vasut add r1, r10, r1 /* r1 <- address of symbol in table */ 2386e96cf9aSMarek Vasut ldr r1, [r1, #4] /* r1 <- symbol value */ 2393600945bSWolfgang Denk add r1, r1, r9 /* r1 <- relocated sym addr */ 2406e96cf9aSMarek Vasut b fixnext 2416e96cf9aSMarek Vasutfixrel: 2426e96cf9aSMarek Vasut /* relative fix: increase location by offset */ 2436e96cf9aSMarek Vasut ldr r1, [r0] 2446e96cf9aSMarek Vasut add r1, r1, r9 2456e96cf9aSMarek Vasutfixnext: 2466e96cf9aSMarek Vasut str r1, [r0] 2476e96cf9aSMarek Vasut add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 2485347f68cSHeiko Schocher cmp r2, r3 2496e96cf9aSMarek Vasut blo fixloop 25020f7b1b7SMarek Vasut#endif 2515347f68cSHeiko Schocher 2525347f68cSHeiko Schocherclear_bss: 253401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 2546e96cf9aSMarek Vasut ldr r0, _bss_start_ofs 2556e96cf9aSMarek Vasut ldr r1, _bss_end_ofs 256a78fb68fSAndreas Bießmann mov r4, r6 /* reloc addr */ 2575347f68cSHeiko Schocher add r0, r0, r4 2585347f68cSHeiko Schocher add r1, r1, r4 2595347f68cSHeiko Schocher mov r2, #0x00000000 /* clear */ 2605347f68cSHeiko Schocher 2615347f68cSHeiko Schocherclbss_l:str r2, [r0] /* clear loop... */ 2625347f68cSHeiko Schocher add r0, r0, #4 2635347f68cSHeiko Schocher cmp r0, r1 2645347f68cSHeiko Schocher bne clbss_l 265401bb30bSAneesh V#endif /* #ifndef CONFIG_SPL_BUILD */ 2665347f68cSHeiko Schocher 2675347f68cSHeiko Schocher/* 2685347f68cSHeiko Schocher * We are done. Do not return, instead branch to second part of board 2695347f68cSHeiko Schocher * initialization, now running from RAM. 2705347f68cSHeiko Schocher */ 27120f7b1b7SMarek Vasut#ifdef CONFIG_ONENAND_SPL 27220f7b1b7SMarek Vasut ldr r0, _onenand_boot_ofs 2736e96cf9aSMarek Vasut mov pc, r0 2745347f68cSHeiko Schocher 27520f7b1b7SMarek Vasut_onenand_boot_ofs: 27620f7b1b7SMarek Vasut .word onenand_boot 2775347f68cSHeiko Schocher#else 27820f7b1b7SMarek Vasutjump_2_ram: 2796e96cf9aSMarek Vasut ldr r0, _board_init_r_ofs 28020f7b1b7SMarek Vasut ldr r1, _TEXT_BASE 281123fb7deSDarius Augulis add lr, r0, r1 282123fb7deSDarius Augulis add lr, lr, r9 2835347f68cSHeiko Schocher /* setup parameters for board_init_r */ 2845347f68cSHeiko Schocher mov r0, r5 /* gd_t */ 285a78fb68fSAndreas Bießmann mov r1, r6 /* dest_addr */ 2865347f68cSHeiko Schocher /* jump to it ... */ 2875347f68cSHeiko Schocher mov pc, lr 2885347f68cSHeiko Schocher 2896e96cf9aSMarek Vasut_board_init_r_ofs: 2906e96cf9aSMarek Vasut .word board_init_r - _start 29120f7b1b7SMarek Vasut#endif 2925347f68cSHeiko Schocher 2936e96cf9aSMarek Vasut_rel_dyn_start_ofs: 2946e96cf9aSMarek Vasut .word __rel_dyn_start - _start 2956e96cf9aSMarek Vasut_rel_dyn_end_ofs: 2966e96cf9aSMarek Vasut .word __rel_dyn_end - _start 2976e96cf9aSMarek Vasut_dynsym_start_ofs: 2986e96cf9aSMarek Vasut .word __dynsym_start - _start 2992cad92fdSMarek Vasut#endif 30020f7b1b7SMarek Vasut/* 30120f7b1b7SMarek Vasut ************************************************************************* 30220f7b1b7SMarek Vasut * 30320f7b1b7SMarek Vasut * CPU_init_critical registers 30420f7b1b7SMarek Vasut * 30520f7b1b7SMarek Vasut * setup important registers 30620f7b1b7SMarek Vasut * setup memory timing 30720f7b1b7SMarek Vasut * 30820f7b1b7SMarek Vasut ************************************************************************* 30920f7b1b7SMarek Vasut */ 310*7f4cfcf4SMarek Vasut#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250) 31120f7b1b7SMarek Vasutcpu_init_crit: 31220f7b1b7SMarek Vasut /* 31320f7b1b7SMarek Vasut * flush v4 I/D caches 31420f7b1b7SMarek Vasut */ 31520f7b1b7SMarek Vasut mov r0, #0 31620f7b1b7SMarek Vasut mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 31720f7b1b7SMarek Vasut mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 3182cad92fdSMarek Vasut 31920f7b1b7SMarek Vasut /* 32020f7b1b7SMarek Vasut * disable MMU stuff and caches 32120f7b1b7SMarek Vasut */ 32220f7b1b7SMarek Vasut mrc p15, 0, r0, c1, c0, 0 32320f7b1b7SMarek Vasut bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 32420f7b1b7SMarek Vasut bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 32520f7b1b7SMarek Vasut orr r0, r0, #0x00000002 @ set bit 2 (A) Align 32620f7b1b7SMarek Vasut orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 32720f7b1b7SMarek Vasut mcr p15, 0, r0, c1, c0, 0 32884ad6884SPeter Tyser 32920f7b1b7SMarek Vasut mov pc, lr /* back to my caller */ 330*7f4cfcf4SMarek Vasut#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */ 33184ad6884SPeter Tyser 332401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 33320f7b1b7SMarek Vasut/* 33420f7b1b7SMarek Vasut ************************************************************************* 33520f7b1b7SMarek Vasut * 33620f7b1b7SMarek Vasut * Interrupt handling 33720f7b1b7SMarek Vasut * 33820f7b1b7SMarek Vasut ************************************************************************* 33920f7b1b7SMarek Vasut */ 34020f7b1b7SMarek Vasut@ 34120f7b1b7SMarek Vasut@ IRQ stack frame. 34220f7b1b7SMarek Vasut@ 34384ad6884SPeter Tyser#define S_FRAME_SIZE 72 34484ad6884SPeter Tyser 34584ad6884SPeter Tyser#define S_OLD_R0 68 34684ad6884SPeter Tyser#define S_PSR 64 34784ad6884SPeter Tyser#define S_PC 60 34884ad6884SPeter Tyser#define S_LR 56 34984ad6884SPeter Tyser#define S_SP 52 35084ad6884SPeter Tyser 35184ad6884SPeter Tyser#define S_IP 48 35284ad6884SPeter Tyser#define S_FP 44 35384ad6884SPeter Tyser#define S_R10 40 35484ad6884SPeter Tyser#define S_R9 36 35584ad6884SPeter Tyser#define S_R8 32 35684ad6884SPeter Tyser#define S_R7 28 35784ad6884SPeter Tyser#define S_R6 24 35884ad6884SPeter Tyser#define S_R5 20 35984ad6884SPeter Tyser#define S_R4 16 36084ad6884SPeter Tyser#define S_R3 12 36184ad6884SPeter Tyser#define S_R2 8 36284ad6884SPeter Tyser#define S_R1 4 36384ad6884SPeter Tyser#define S_R0 0 36484ad6884SPeter Tyser 36584ad6884SPeter Tyser#define MODE_SVC 0x13 36620f7b1b7SMarek Vasut#define I_BIT 0x80 36784ad6884SPeter Tyser 36820f7b1b7SMarek Vasut/* 36920f7b1b7SMarek Vasut * use bad_save_user_regs for abort/prefetch/undef/swi ... 37020f7b1b7SMarek Vasut * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 37120f7b1b7SMarek Vasut */ 37284ad6884SPeter Tyser 37384ad6884SPeter Tyser .macro bad_save_user_regs 37420f7b1b7SMarek Vasut sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 37520f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 37684ad6884SPeter Tyser 37720f7b1b7SMarek Vasut ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 37820f7b1b7SMarek Vasut ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 37920f7b1b7SMarek Vasut add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 38084ad6884SPeter Tyser 38184ad6884SPeter Tyser add r5, sp, #S_SP 38284ad6884SPeter Tyser mov r1, lr 38320f7b1b7SMarek Vasut stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 38420f7b1b7SMarek Vasut mov r0, sp @ save current stack into r0 (param register) 38584ad6884SPeter Tyser .endm 38684ad6884SPeter Tyser 38784ad6884SPeter Tyser .macro irq_save_user_regs 38884ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 38920f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Calling r0-r12 39020f7b1b7SMarek Vasut add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 39120f7b1b7SMarek Vasut stmdb r8, {sp, lr}^ @ Calling SP, LR 39220f7b1b7SMarek Vasut str lr, [r8, #0] @ Save calling PC 39384ad6884SPeter Tyser mrs r6, spsr 39420f7b1b7SMarek Vasut str r6, [r8, #4] @ Save CPSR 39520f7b1b7SMarek Vasut str r0, [r8, #8] @ Save OLD_R0 39684ad6884SPeter Tyser mov r0, sp 39784ad6884SPeter Tyser .endm 39884ad6884SPeter Tyser 39984ad6884SPeter Tyser .macro irq_restore_user_regs 40084ad6884SPeter Tyser ldmia sp, {r0 - lr}^ @ Calling r0 - lr 40184ad6884SPeter Tyser mov r0, r0 40284ad6884SPeter Tyser ldr lr, [sp, #S_PC] @ Get PC 40384ad6884SPeter Tyser add sp, sp, #S_FRAME_SIZE 40484ad6884SPeter Tyser subs pc, lr, #4 @ return & move spsr_svc into cpsr 40584ad6884SPeter Tyser .endm 40684ad6884SPeter Tyser 40784ad6884SPeter Tyser .macro get_bad_stack 40820f7b1b7SMarek Vasut ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 40984ad6884SPeter Tyser 41020f7b1b7SMarek Vasut str lr, [r13] @ save caller lr in position 0 of saved stack 41120f7b1b7SMarek Vasut mrs lr, spsr @ get the spsr 41220f7b1b7SMarek Vasut str lr, [r13, #4] @ save spsr in position 1 of saved stack 41384ad6884SPeter Tyser 41484ad6884SPeter Tyser mov r13, #MODE_SVC @ prepare SVC-Mode 41520f7b1b7SMarek Vasut @ msr spsr_c, r13 41620f7b1b7SMarek Vasut msr spsr, r13 @ switch modes, make sure moves will execute 41720f7b1b7SMarek Vasut mov lr, pc @ capture return pc 41820f7b1b7SMarek Vasut movs pc, lr @ jump to next instruction & switch modes. 41920f7b1b7SMarek Vasut .endm 42020f7b1b7SMarek Vasut 42120f7b1b7SMarek Vasut .macro get_bad_stack_swi 42220f7b1b7SMarek Vasut sub r13, r13, #4 @ space on current stack for scratch reg. 42320f7b1b7SMarek Vasut str r0, [r13] @ save R0's value. 42420f7b1b7SMarek Vasut ldr r0, IRQ_STACK_START_IN @ get data regions start 42520f7b1b7SMarek Vasut str lr, [r0] @ save caller lr in position 0 of saved stack 42620f7b1b7SMarek Vasut mrs r0, spsr @ get the spsr 42720f7b1b7SMarek Vasut str lr, [r0, #4] @ save spsr in position 1 of saved stack 42820f7b1b7SMarek Vasut ldr r0, [r13] @ restore r0 42920f7b1b7SMarek Vasut add r13, r13, #4 @ pop stack entry 43084ad6884SPeter Tyser .endm 43184ad6884SPeter Tyser 43284ad6884SPeter Tyser .macro get_irq_stack @ setup IRQ stack 43384ad6884SPeter Tyser ldr sp, IRQ_STACK_START 43484ad6884SPeter Tyser .endm 43584ad6884SPeter Tyser 43684ad6884SPeter Tyser .macro get_fiq_stack @ setup FIQ stack 43784ad6884SPeter Tyser ldr sp, FIQ_STACK_START 43884ad6884SPeter Tyser .endm 43920f7b1b7SMarek Vasut#endif /* CONFIG_SPL_BUILD */ 44084ad6884SPeter Tyser 44120f7b1b7SMarek Vasut/* 44220f7b1b7SMarek Vasut * exception handlers 44320f7b1b7SMarek Vasut */ 444401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 4455ab877b6SMarek Vasut .align 5 4465ab877b6SMarek Vasutdo_hang: 44720f7b1b7SMarek Vasut ldr sp, _TEXT_BASE /* use 32 words about stack */ 4485ab877b6SMarek Vasut bl hang /* hang and never return */ 44920f7b1b7SMarek Vasut#else /* !CONFIG_SPL_BUILD */ 45084ad6884SPeter Tyser .align 5 45184ad6884SPeter Tyserundefined_instruction: 45284ad6884SPeter Tyser get_bad_stack 45384ad6884SPeter Tyser bad_save_user_regs 45484ad6884SPeter Tyser bl do_undefined_instruction 45584ad6884SPeter Tyser 45684ad6884SPeter Tyser .align 5 45784ad6884SPeter Tysersoftware_interrupt: 45820f7b1b7SMarek Vasut get_bad_stack_swi 45984ad6884SPeter Tyser bad_save_user_regs 46084ad6884SPeter Tyser bl do_software_interrupt 46184ad6884SPeter Tyser 46284ad6884SPeter Tyser .align 5 46384ad6884SPeter Tyserprefetch_abort: 46484ad6884SPeter Tyser get_bad_stack 46584ad6884SPeter Tyser bad_save_user_regs 46684ad6884SPeter Tyser bl do_prefetch_abort 46784ad6884SPeter Tyser 46884ad6884SPeter Tyser .align 5 46984ad6884SPeter Tyserdata_abort: 47084ad6884SPeter Tyser get_bad_stack 47184ad6884SPeter Tyser bad_save_user_regs 47284ad6884SPeter Tyser bl do_data_abort 47384ad6884SPeter Tyser 47484ad6884SPeter Tyser .align 5 47584ad6884SPeter Tysernot_used: 47684ad6884SPeter Tyser get_bad_stack 47784ad6884SPeter Tyser bad_save_user_regs 47884ad6884SPeter Tyser bl do_not_used 47984ad6884SPeter Tyser 48084ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 48184ad6884SPeter Tyser 48284ad6884SPeter Tyser .align 5 48384ad6884SPeter Tyserirq: 48484ad6884SPeter Tyser get_irq_stack 48584ad6884SPeter Tyser irq_save_user_regs 48684ad6884SPeter Tyser bl do_irq 48784ad6884SPeter Tyser irq_restore_user_regs 48884ad6884SPeter Tyser 48984ad6884SPeter Tyser .align 5 49084ad6884SPeter Tyserfiq: 49184ad6884SPeter Tyser get_fiq_stack 49220f7b1b7SMarek Vasut /* someone ought to write a more effiction fiq_save_user_regs */ 49320f7b1b7SMarek Vasut irq_save_user_regs 49420f7b1b7SMarek Vasut bl do_fiq 49584ad6884SPeter Tyser irq_restore_user_regs 49684ad6884SPeter Tyser 49720f7b1b7SMarek Vasut#else 49884ad6884SPeter Tyser 49984ad6884SPeter Tyser .align 5 50084ad6884SPeter Tyserirq: 50184ad6884SPeter Tyser get_bad_stack 50284ad6884SPeter Tyser bad_save_user_regs 50384ad6884SPeter Tyser bl do_irq 50484ad6884SPeter Tyser 50584ad6884SPeter Tyser .align 5 50684ad6884SPeter Tyserfiq: 50784ad6884SPeter Tyser get_bad_stack 50884ad6884SPeter Tyser bad_save_user_regs 50984ad6884SPeter Tyser bl do_fiq 51084ad6884SPeter Tyser 51120f7b1b7SMarek Vasut#endif 51284ad6884SPeter Tyser .align 5 513401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 514*7f4cfcf4SMarek Vasut 515*7f4cfcf4SMarek Vasut 516*7f4cfcf4SMarek Vasut/* 517*7f4cfcf4SMarek Vasut * Enable MMU to use DCache as DRAM. 518*7f4cfcf4SMarek Vasut * 519*7f4cfcf4SMarek Vasut * This is useful on PXA25x and PXA26x in early bootstages, where there is no 520*7f4cfcf4SMarek Vasut * other possible memory available to hold stack. 521*7f4cfcf4SMarek Vasut */ 522*7f4cfcf4SMarek Vasut#ifdef CONFIG_PXA250 523*7f4cfcf4SMarek Vasut.macro CPWAIT reg 524*7f4cfcf4SMarek Vasut mrc p15, 0, \reg, c2, c0, 0 525*7f4cfcf4SMarek Vasut mov \reg, \reg 526*7f4cfcf4SMarek Vasut sub pc, pc, #4 527*7f4cfcf4SMarek Vasut.endm 528*7f4cfcf4SMarek Vasutlock_cache_for_stack: 529*7f4cfcf4SMarek Vasut /* Domain access -- enable for all CPs */ 530*7f4cfcf4SMarek Vasut ldr r0, =0x0000ffff 531*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c3, c0, 0 532*7f4cfcf4SMarek Vasut 533*7f4cfcf4SMarek Vasut /* Point TTBR to MMU table */ 534*7f4cfcf4SMarek Vasut ldr r0, =mmutable 535*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c2, c0, 0 536*7f4cfcf4SMarek Vasut 537*7f4cfcf4SMarek Vasut /* Kick in MMU, ICache, DCache, BTB */ 538*7f4cfcf4SMarek Vasut mrc p15, 0, r0, c1, c0, 0 539*7f4cfcf4SMarek Vasut bic r0, #0x1b00 540*7f4cfcf4SMarek Vasut bic r0, #0x0087 541*7f4cfcf4SMarek Vasut orr r0, #0x1800 542*7f4cfcf4SMarek Vasut orr r0, #0x0005 543*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c1, c0, 0 544*7f4cfcf4SMarek Vasut CPWAIT r0 545*7f4cfcf4SMarek Vasut 546*7f4cfcf4SMarek Vasut /* Unlock Icache, Dcache */ 547*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c1, 1 548*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 1 549*7f4cfcf4SMarek Vasut 550*7f4cfcf4SMarek Vasut /* Flush Icache, Dcache, BTB */ 551*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c7, 0 552*7f4cfcf4SMarek Vasut 553*7f4cfcf4SMarek Vasut /* Unlock I-TLB, D-TLB */ 554*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c4, 1 555*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c8, 1 556*7f4cfcf4SMarek Vasut 557*7f4cfcf4SMarek Vasut /* Flush TLB */ 558*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c8, c7, 0 559*7f4cfcf4SMarek Vasut 560*7f4cfcf4SMarek Vasut /* Allocate 4096 bytes of Dcache as RAM */ 561*7f4cfcf4SMarek Vasut 562*7f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 563*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 564*7f4cfcf4SMarek Vasut 565*7f4cfcf4SMarek Vasut mov r4, #0x00 566*7f4cfcf4SMarek Vasut mov r5, #0x00 567*7f4cfcf4SMarek Vasut mov r2, #0x01 568*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 0 569*7f4cfcf4SMarek Vasut CPWAIT r0 570*7f4cfcf4SMarek Vasut 571*7f4cfcf4SMarek Vasut /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 572*7f4cfcf4SMarek Vasut mov r0, #128 573*7f4cfcf4SMarek Vasut ldr r1, =0xfffff000 574*7f4cfcf4SMarek Vasut 575*7f4cfcf4SMarek Vasutalloc: 576*7f4cfcf4SMarek Vasut mcr p15, 0, r1, c7, c2, 5 577*7f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 578*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 579*7f4cfcf4SMarek Vasut strd r4, [r1], #8 580*7f4cfcf4SMarek Vasut strd r4, [r1], #8 581*7f4cfcf4SMarek Vasut strd r4, [r1], #8 582*7f4cfcf4SMarek Vasut strd r4, [r1], #8 583*7f4cfcf4SMarek Vasut subs r0, #0x01 584*7f4cfcf4SMarek Vasut bne alloc 585*7f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 586*7f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 587*7f4cfcf4SMarek Vasut mov r2, #0x00 588*7f4cfcf4SMarek Vasut mcr p15, 0, r2, c9, c2, 0 589*7f4cfcf4SMarek Vasut CPWAIT r0 590*7f4cfcf4SMarek Vasut 591*7f4cfcf4SMarek Vasut mov pc, lr 592*7f4cfcf4SMarek Vasut 593*7f4cfcf4SMarek Vasut.section .mmutable, "a" 594*7f4cfcf4SMarek Vasutmmutable: 595*7f4cfcf4SMarek Vasut .align 14 596*7f4cfcf4SMarek Vasut /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 597*7f4cfcf4SMarek Vasut .set __base, 0 598*7f4cfcf4SMarek Vasut .rept 0xfff 599*7f4cfcf4SMarek Vasut .word (__base << 20) | 0xc12 600*7f4cfcf4SMarek Vasut .set __base, __base + 1 601*7f4cfcf4SMarek Vasut .endr 602*7f4cfcf4SMarek Vasut 603*7f4cfcf4SMarek Vasut /* 0xfff00000 : 1:1, cached mapping */ 604*7f4cfcf4SMarek Vasut .word (0xfff << 20) | 0x1c1e 605*7f4cfcf4SMarek Vasut#endif /* CONFIG_PXA250 */ 606