184ad6884SPeter Tyser/* 220f7b1b7SMarek Vasut * armboot - Startup Code for XScale CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 584ad6884SPeter Tyser * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 684ad6884SPeter Tyser * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 784ad6884SPeter Tyser * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 820f7b1b7SMarek Vasut * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 920f7b1b7SMarek Vasut * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 1020f7b1b7SMarek Vasut * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 1284ad6884SPeter Tyser * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 1320f7b1b7SMarek Vasut * Copyright (C) 2003 Kshitij <kshitij@ti.com> 1420f7b1b7SMarek Vasut * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 1520f7b1b7SMarek Vasut * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 1620f7b1b7SMarek Vasut * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 1720f7b1b7SMarek Vasut * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 1884ad6884SPeter Tyser * 1984ad6884SPeter Tyser * See file CREDITS for list of people who contributed to this 2084ad6884SPeter Tyser * project. 2184ad6884SPeter Tyser * 2284ad6884SPeter Tyser * This program is free software; you can redistribute it and/or 2384ad6884SPeter Tyser * modify it under the terms of the GNU General Public License as 2484ad6884SPeter Tyser * published by the Free Software Foundation; either version 2 of 2584ad6884SPeter Tyser * the License, or (at your option) any later version. 2684ad6884SPeter Tyser * 2784ad6884SPeter Tyser * This program is distributed in the hope that it will be useful, 2884ad6884SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 2984ad6884SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 3084ad6884SPeter Tyser * GNU General Public License for more details. 3184ad6884SPeter Tyser * 3284ad6884SPeter Tyser * You should have received a copy of the GNU General Public License 3384ad6884SPeter Tyser * along with this program; if not, write to the Free Software 3484ad6884SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3584ad6884SPeter Tyser * MA 02111-1307 USA 3684ad6884SPeter Tyser */ 3784ad6884SPeter Tyser 3825ddd1fbSWolfgang Denk#include <asm-offsets.h> 3984ad6884SPeter Tyser#include <config.h> 4084ad6884SPeter Tyser#include <version.h> 417f4cfcf4SMarek Vasut 42abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 437f4cfcf4SMarek Vasut#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 447f4cfcf4SMarek Vasut#error "Init SP address must be set to 0xfffff800 for PXA250" 457f4cfcf4SMarek Vasut#endif 467f4cfcf4SMarek Vasut#endif 477f4cfcf4SMarek Vasut 4884ad6884SPeter Tyser.globl _start 4984ad6884SPeter Tyser_start: b reset 50401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 515ab877b6SMarek Vasut ldr pc, _hang 525ab877b6SMarek Vasut ldr pc, _hang 535ab877b6SMarek Vasut ldr pc, _hang 545ab877b6SMarek Vasut ldr pc, _hang 555ab877b6SMarek Vasut ldr pc, _hang 565ab877b6SMarek Vasut ldr pc, _hang 575ab877b6SMarek Vasut ldr pc, _hang 585ab877b6SMarek Vasut 595ab877b6SMarek Vasut_hang: 605ab877b6SMarek Vasut .word do_hang 615ab877b6SMarek Vasut .word 0x12345678 625ab877b6SMarek Vasut .word 0x12345678 635ab877b6SMarek Vasut .word 0x12345678 645ab877b6SMarek Vasut .word 0x12345678 655ab877b6SMarek Vasut .word 0x12345678 665ab877b6SMarek Vasut .word 0x12345678 675ab877b6SMarek Vasut .word 0x12345678 /* now 16*4=64 */ 685ab877b6SMarek Vasut#else 6984ad6884SPeter Tyser ldr pc, _undefined_instruction 7084ad6884SPeter Tyser ldr pc, _software_interrupt 7184ad6884SPeter Tyser ldr pc, _prefetch_abort 7284ad6884SPeter Tyser ldr pc, _data_abort 7384ad6884SPeter Tyser ldr pc, _not_used 7484ad6884SPeter Tyser ldr pc, _irq 7584ad6884SPeter Tyser ldr pc, _fiq 7684ad6884SPeter Tyser 7784ad6884SPeter Tyser_undefined_instruction: .word undefined_instruction 7884ad6884SPeter Tyser_software_interrupt: .word software_interrupt 7984ad6884SPeter Tyser_prefetch_abort: .word prefetch_abort 8084ad6884SPeter Tyser_data_abort: .word data_abort 8184ad6884SPeter Tyser_not_used: .word not_used 8284ad6884SPeter Tyser_irq: .word irq 8384ad6884SPeter Tyser_fiq: .word fiq 8420f7b1b7SMarek Vasut_pad: .word 0x12345678 /* now 16*4=64 */ 85401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 8620f7b1b7SMarek Vasut.global _end_vect 8720f7b1b7SMarek Vasut_end_vect: 8884ad6884SPeter Tyser 8984ad6884SPeter Tyser .balignl 16,0xdeadbeef 9084ad6884SPeter Tyser/* 9120f7b1b7SMarek Vasut ************************************************************************* 9220f7b1b7SMarek Vasut * 9384ad6884SPeter Tyser * Startup Code (reset vector) 9484ad6884SPeter Tyser * 9520f7b1b7SMarek Vasut * do important init only if we don't start from memory! 9620f7b1b7SMarek Vasut * setup Memory and board specific bits prior to relocation. 9720f7b1b7SMarek Vasut * relocate armboot to ram 9820f7b1b7SMarek Vasut * setup stack 9920f7b1b7SMarek Vasut * 10020f7b1b7SMarek Vasut ************************************************************************* 10184ad6884SPeter Tyser */ 10284ad6884SPeter Tyser 1035347f68cSHeiko Schocher.globl _TEXT_BASE 10484ad6884SPeter Tyser_TEXT_BASE: 105508611bcSBenoît Thébaudeau#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 10620f7b1b7SMarek Vasut .word CONFIG_SPL_TEXT_BASE 10720f7b1b7SMarek Vasut#else 10814d0a02aSWolfgang Denk .word CONFIG_SYS_TEXT_BASE 10920f7b1b7SMarek Vasut#endif 11084ad6884SPeter Tyser 11184ad6884SPeter Tyser/* 11284ad6884SPeter Tyser * These are defined in the board-specific linker script. 11320f7b1b7SMarek Vasut * Subtracting _start from them lets the linker put their 11420f7b1b7SMarek Vasut * relative position in the executable instead of leaving 11520f7b1b7SMarek Vasut * them null. 11684ad6884SPeter Tyser */ 1176e96cf9aSMarek Vasut.globl _bss_start_ofs 1186e96cf9aSMarek Vasut_bss_start_ofs: 1196e96cf9aSMarek Vasut .word __bss_start - _start 12084ad6884SPeter Tyser 1216e96cf9aSMarek Vasut.globl _bss_end_ofs 1226e96cf9aSMarek Vasut_bss_end_ofs: 1233929fb0aSSimon Glass .word __bss_end - _start 12484ad6884SPeter Tyser 125f326cbbaSPo-Yu Chuang.globl _end_ofs 126f326cbbaSPo-Yu Chuang_end_ofs: 127f326cbbaSPo-Yu Chuang .word _end - _start 128f326cbbaSPo-Yu Chuang 12984ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 13084ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 13184ad6884SPeter Tyser.globl IRQ_STACK_START 13284ad6884SPeter TyserIRQ_STACK_START: 13384ad6884SPeter Tyser .word 0x0badc0de 13484ad6884SPeter Tyser 13584ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 13684ad6884SPeter Tyser.globl FIQ_STACK_START 13784ad6884SPeter TyserFIQ_STACK_START: 13884ad6884SPeter Tyser .word 0x0badc0de 13920f7b1b7SMarek Vasut#endif 14084ad6884SPeter Tyser 1415347f68cSHeiko Schocher/* IRQ stack memory (calculated at run-time) + 8 bytes */ 1425347f68cSHeiko Schocher.globl IRQ_STACK_START_IN 1435347f68cSHeiko SchocherIRQ_STACK_START_IN: 1445347f68cSHeiko Schocher .word 0x0badc0de 1455347f68cSHeiko Schocher 1465347f68cSHeiko Schocher/* 1475347f68cSHeiko Schocher * the actual reset code 1485347f68cSHeiko Schocher */ 1495347f68cSHeiko Schocher 1505347f68cSHeiko Schocherreset: 1515347f68cSHeiko Schocher /* 1525347f68cSHeiko Schocher * set the cpu to SVC32 mode 1535347f68cSHeiko Schocher */ 1545347f68cSHeiko Schocher mrs r0,cpsr 1555347f68cSHeiko Schocher bic r0,r0,#0x1f 1565347f68cSHeiko Schocher orr r0,r0,#0xd3 1575347f68cSHeiko Schocher msr cpsr,r0 1585347f68cSHeiko Schocher 15920f7b1b7SMarek Vasut#ifndef CONFIG_SKIP_LOWLEVEL_INIT 16020f7b1b7SMarek Vasut bl cpu_init_crit 16120f7b1b7SMarek Vasut#endif 1625347f68cSHeiko Schocher 163abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 1647f4cfcf4SMarek Vasut bl lock_cache_for_stack 1657f4cfcf4SMarek Vasut#endif 1667f4cfcf4SMarek Vasut 167e05e5de7SAlbert ARIBAUD bl _main 1685347f68cSHeiko Schocher 1695347f68cSHeiko Schocher/*------------------------------------------------------------------------------*/ 170e05e5de7SAlbert ARIBAUD 171e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 172e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 173e05e5de7SAlbert ARIBAUD 174*3da0e575SAlbert ARIBAUD#ifdef CONFIG_CPU_PXA25X 175*3da0e575SAlbert ARIBAUD /* 176*3da0e575SAlbert ARIBAUD * Unlock (actually, disable) the cache now that board_init_f 177*3da0e575SAlbert ARIBAUD * is done. We could do this earlier but we would need to add 178*3da0e575SAlbert ARIBAUD * a new C runtime hook, whereas c_runtime_cpu_setup already 179*3da0e575SAlbert ARIBAUD * exists. 180*3da0e575SAlbert ARIBAUD * As this routine is just a call to cpu_init_crit, let us 181*3da0e575SAlbert ARIBAUD * tail-optimize and do a simple branch here. 182*3da0e575SAlbert ARIBAUD */ 183*3da0e575SAlbert ARIBAUD b cpu_init_crit 184*3da0e575SAlbert ARIBAUD#else 185e05e5de7SAlbert ARIBAUD bx lr 186*3da0e575SAlbert ARIBAUD#endif 187e05e5de7SAlbert ARIBAUD 18820f7b1b7SMarek Vasut/* 18920f7b1b7SMarek Vasut ************************************************************************* 19020f7b1b7SMarek Vasut * 19120f7b1b7SMarek Vasut * CPU_init_critical registers 19220f7b1b7SMarek Vasut * 19320f7b1b7SMarek Vasut * setup important registers 19420f7b1b7SMarek Vasut * setup memory timing 19520f7b1b7SMarek Vasut * 19620f7b1b7SMarek Vasut ************************************************************************* 19720f7b1b7SMarek Vasut */ 198abc20abaSMarek Vasut#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 19920f7b1b7SMarek Vasutcpu_init_crit: 20020f7b1b7SMarek Vasut /* 20120f7b1b7SMarek Vasut * flush v4 I/D caches 20220f7b1b7SMarek Vasut */ 20320f7b1b7SMarek Vasut mov r0, #0 20420f7b1b7SMarek Vasut mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 20520f7b1b7SMarek Vasut mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 2062cad92fdSMarek Vasut 20720f7b1b7SMarek Vasut /* 20820f7b1b7SMarek Vasut * disable MMU stuff and caches 20920f7b1b7SMarek Vasut */ 21020f7b1b7SMarek Vasut mrc p15, 0, r0, c1, c0, 0 21120f7b1b7SMarek Vasut bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 21220f7b1b7SMarek Vasut bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 21320f7b1b7SMarek Vasut orr r0, r0, #0x00000002 @ set bit 2 (A) Align 21420f7b1b7SMarek Vasut orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 21520f7b1b7SMarek Vasut mcr p15, 0, r0, c1, c0, 0 21684ad6884SPeter Tyser 21720f7b1b7SMarek Vasut mov pc, lr /* back to my caller */ 218abc20abaSMarek Vasut#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 21984ad6884SPeter Tyser 220401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 22120f7b1b7SMarek Vasut/* 22220f7b1b7SMarek Vasut ************************************************************************* 22320f7b1b7SMarek Vasut * 22420f7b1b7SMarek Vasut * Interrupt handling 22520f7b1b7SMarek Vasut * 22620f7b1b7SMarek Vasut ************************************************************************* 22720f7b1b7SMarek Vasut */ 22820f7b1b7SMarek Vasut@ 22920f7b1b7SMarek Vasut@ IRQ stack frame. 23020f7b1b7SMarek Vasut@ 23184ad6884SPeter Tyser#define S_FRAME_SIZE 72 23284ad6884SPeter Tyser 23384ad6884SPeter Tyser#define S_OLD_R0 68 23484ad6884SPeter Tyser#define S_PSR 64 23584ad6884SPeter Tyser#define S_PC 60 23684ad6884SPeter Tyser#define S_LR 56 23784ad6884SPeter Tyser#define S_SP 52 23884ad6884SPeter Tyser 23984ad6884SPeter Tyser#define S_IP 48 24084ad6884SPeter Tyser#define S_FP 44 24184ad6884SPeter Tyser#define S_R10 40 24284ad6884SPeter Tyser#define S_R9 36 24384ad6884SPeter Tyser#define S_R8 32 24484ad6884SPeter Tyser#define S_R7 28 24584ad6884SPeter Tyser#define S_R6 24 24684ad6884SPeter Tyser#define S_R5 20 24784ad6884SPeter Tyser#define S_R4 16 24884ad6884SPeter Tyser#define S_R3 12 24984ad6884SPeter Tyser#define S_R2 8 25084ad6884SPeter Tyser#define S_R1 4 25184ad6884SPeter Tyser#define S_R0 0 25284ad6884SPeter Tyser 25384ad6884SPeter Tyser#define MODE_SVC 0x13 25420f7b1b7SMarek Vasut#define I_BIT 0x80 25584ad6884SPeter Tyser 25620f7b1b7SMarek Vasut/* 25720f7b1b7SMarek Vasut * use bad_save_user_regs for abort/prefetch/undef/swi ... 25820f7b1b7SMarek Vasut * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 25920f7b1b7SMarek Vasut */ 26084ad6884SPeter Tyser 26184ad6884SPeter Tyser .macro bad_save_user_regs 26220f7b1b7SMarek Vasut sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 26320f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 26484ad6884SPeter Tyser 26520f7b1b7SMarek Vasut ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 26620f7b1b7SMarek Vasut ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 26720f7b1b7SMarek Vasut add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 26884ad6884SPeter Tyser 26984ad6884SPeter Tyser add r5, sp, #S_SP 27084ad6884SPeter Tyser mov r1, lr 27120f7b1b7SMarek Vasut stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 27220f7b1b7SMarek Vasut mov r0, sp @ save current stack into r0 (param register) 27384ad6884SPeter Tyser .endm 27484ad6884SPeter Tyser 27584ad6884SPeter Tyser .macro irq_save_user_regs 27684ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 27720f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Calling r0-r12 27820f7b1b7SMarek Vasut add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 27920f7b1b7SMarek Vasut stmdb r8, {sp, lr}^ @ Calling SP, LR 28020f7b1b7SMarek Vasut str lr, [r8, #0] @ Save calling PC 28184ad6884SPeter Tyser mrs r6, spsr 28220f7b1b7SMarek Vasut str r6, [r8, #4] @ Save CPSR 28320f7b1b7SMarek Vasut str r0, [r8, #8] @ Save OLD_R0 28484ad6884SPeter Tyser mov r0, sp 28584ad6884SPeter Tyser .endm 28684ad6884SPeter Tyser 28784ad6884SPeter Tyser .macro irq_restore_user_regs 28884ad6884SPeter Tyser ldmia sp, {r0 - lr}^ @ Calling r0 - lr 28984ad6884SPeter Tyser mov r0, r0 29084ad6884SPeter Tyser ldr lr, [sp, #S_PC] @ Get PC 29184ad6884SPeter Tyser add sp, sp, #S_FRAME_SIZE 29284ad6884SPeter Tyser subs pc, lr, #4 @ return & move spsr_svc into cpsr 29384ad6884SPeter Tyser .endm 29484ad6884SPeter Tyser 29584ad6884SPeter Tyser .macro get_bad_stack 29620f7b1b7SMarek Vasut ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 29784ad6884SPeter Tyser 29820f7b1b7SMarek Vasut str lr, [r13] @ save caller lr in position 0 of saved stack 29920f7b1b7SMarek Vasut mrs lr, spsr @ get the spsr 30020f7b1b7SMarek Vasut str lr, [r13, #4] @ save spsr in position 1 of saved stack 30184ad6884SPeter Tyser 30284ad6884SPeter Tyser mov r13, #MODE_SVC @ prepare SVC-Mode 30320f7b1b7SMarek Vasut @ msr spsr_c, r13 30420f7b1b7SMarek Vasut msr spsr, r13 @ switch modes, make sure moves will execute 30520f7b1b7SMarek Vasut mov lr, pc @ capture return pc 30620f7b1b7SMarek Vasut movs pc, lr @ jump to next instruction & switch modes. 30720f7b1b7SMarek Vasut .endm 30820f7b1b7SMarek Vasut 30920f7b1b7SMarek Vasut .macro get_bad_stack_swi 31020f7b1b7SMarek Vasut sub r13, r13, #4 @ space on current stack for scratch reg. 31120f7b1b7SMarek Vasut str r0, [r13] @ save R0's value. 31220f7b1b7SMarek Vasut ldr r0, IRQ_STACK_START_IN @ get data regions start 31320f7b1b7SMarek Vasut str lr, [r0] @ save caller lr in position 0 of saved stack 3144411b2aeSTetsuyuki Kobayashi mrs lr, spsr @ get the spsr 31520f7b1b7SMarek Vasut str lr, [r0, #4] @ save spsr in position 1 of saved stack 3164411b2aeSTetsuyuki Kobayashi ldr lr, [r0] @ restore lr 31720f7b1b7SMarek Vasut ldr r0, [r13] @ restore r0 31820f7b1b7SMarek Vasut add r13, r13, #4 @ pop stack entry 31984ad6884SPeter Tyser .endm 32084ad6884SPeter Tyser 32184ad6884SPeter Tyser .macro get_irq_stack @ setup IRQ stack 32284ad6884SPeter Tyser ldr sp, IRQ_STACK_START 32384ad6884SPeter Tyser .endm 32484ad6884SPeter Tyser 32584ad6884SPeter Tyser .macro get_fiq_stack @ setup FIQ stack 32684ad6884SPeter Tyser ldr sp, FIQ_STACK_START 32784ad6884SPeter Tyser .endm 32820f7b1b7SMarek Vasut#endif /* CONFIG_SPL_BUILD */ 32984ad6884SPeter Tyser 33020f7b1b7SMarek Vasut/* 33120f7b1b7SMarek Vasut * exception handlers 33220f7b1b7SMarek Vasut */ 333401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 3345ab877b6SMarek Vasut .align 5 3355ab877b6SMarek Vasutdo_hang: 33620f7b1b7SMarek Vasut ldr sp, _TEXT_BASE /* use 32 words about stack */ 3375ab877b6SMarek Vasut bl hang /* hang and never return */ 33820f7b1b7SMarek Vasut#else /* !CONFIG_SPL_BUILD */ 33984ad6884SPeter Tyser .align 5 34084ad6884SPeter Tyserundefined_instruction: 34184ad6884SPeter Tyser get_bad_stack 34284ad6884SPeter Tyser bad_save_user_regs 34384ad6884SPeter Tyser bl do_undefined_instruction 34484ad6884SPeter Tyser 34584ad6884SPeter Tyser .align 5 34684ad6884SPeter Tysersoftware_interrupt: 34720f7b1b7SMarek Vasut get_bad_stack_swi 34884ad6884SPeter Tyser bad_save_user_regs 34984ad6884SPeter Tyser bl do_software_interrupt 35084ad6884SPeter Tyser 35184ad6884SPeter Tyser .align 5 35284ad6884SPeter Tyserprefetch_abort: 35384ad6884SPeter Tyser get_bad_stack 35484ad6884SPeter Tyser bad_save_user_regs 35584ad6884SPeter Tyser bl do_prefetch_abort 35684ad6884SPeter Tyser 35784ad6884SPeter Tyser .align 5 35884ad6884SPeter Tyserdata_abort: 35984ad6884SPeter Tyser get_bad_stack 36084ad6884SPeter Tyser bad_save_user_regs 36184ad6884SPeter Tyser bl do_data_abort 36284ad6884SPeter Tyser 36384ad6884SPeter Tyser .align 5 36484ad6884SPeter Tysernot_used: 36584ad6884SPeter Tyser get_bad_stack 36684ad6884SPeter Tyser bad_save_user_regs 36784ad6884SPeter Tyser bl do_not_used 36884ad6884SPeter Tyser 36984ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 37084ad6884SPeter Tyser 37184ad6884SPeter Tyser .align 5 37284ad6884SPeter Tyserirq: 37384ad6884SPeter Tyser get_irq_stack 37484ad6884SPeter Tyser irq_save_user_regs 37584ad6884SPeter Tyser bl do_irq 37684ad6884SPeter Tyser irq_restore_user_regs 37784ad6884SPeter Tyser 37884ad6884SPeter Tyser .align 5 37984ad6884SPeter Tyserfiq: 38084ad6884SPeter Tyser get_fiq_stack 38120f7b1b7SMarek Vasut /* someone ought to write a more effiction fiq_save_user_regs */ 38220f7b1b7SMarek Vasut irq_save_user_regs 38320f7b1b7SMarek Vasut bl do_fiq 38484ad6884SPeter Tyser irq_restore_user_regs 38584ad6884SPeter Tyser 38620f7b1b7SMarek Vasut#else 38784ad6884SPeter Tyser 38884ad6884SPeter Tyser .align 5 38984ad6884SPeter Tyserirq: 39084ad6884SPeter Tyser get_bad_stack 39184ad6884SPeter Tyser bad_save_user_regs 39284ad6884SPeter Tyser bl do_irq 39384ad6884SPeter Tyser 39484ad6884SPeter Tyser .align 5 39584ad6884SPeter Tyserfiq: 39684ad6884SPeter Tyser get_bad_stack 39784ad6884SPeter Tyser bad_save_user_regs 39884ad6884SPeter Tyser bl do_fiq 39984ad6884SPeter Tyser 40020f7b1b7SMarek Vasut#endif 40184ad6884SPeter Tyser .align 5 402401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 4037f4cfcf4SMarek Vasut 4047f4cfcf4SMarek Vasut 4057f4cfcf4SMarek Vasut/* 4067f4cfcf4SMarek Vasut * Enable MMU to use DCache as DRAM. 4077f4cfcf4SMarek Vasut * 4087f4cfcf4SMarek Vasut * This is useful on PXA25x and PXA26x in early bootstages, where there is no 4097f4cfcf4SMarek Vasut * other possible memory available to hold stack. 4107f4cfcf4SMarek Vasut */ 411abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 4127f4cfcf4SMarek Vasut.macro CPWAIT reg 4137f4cfcf4SMarek Vasut mrc p15, 0, \reg, c2, c0, 0 4147f4cfcf4SMarek Vasut mov \reg, \reg 4157f4cfcf4SMarek Vasut sub pc, pc, #4 4167f4cfcf4SMarek Vasut.endm 4177f4cfcf4SMarek Vasutlock_cache_for_stack: 4187f4cfcf4SMarek Vasut /* Domain access -- enable for all CPs */ 4197f4cfcf4SMarek Vasut ldr r0, =0x0000ffff 4207f4cfcf4SMarek Vasut mcr p15, 0, r0, c3, c0, 0 4217f4cfcf4SMarek Vasut 4227f4cfcf4SMarek Vasut /* Point TTBR to MMU table */ 4237f4cfcf4SMarek Vasut ldr r0, =mmutable 4247f4cfcf4SMarek Vasut mcr p15, 0, r0, c2, c0, 0 4257f4cfcf4SMarek Vasut 4267f4cfcf4SMarek Vasut /* Kick in MMU, ICache, DCache, BTB */ 4277f4cfcf4SMarek Vasut mrc p15, 0, r0, c1, c0, 0 4287f4cfcf4SMarek Vasut bic r0, #0x1b00 4297f4cfcf4SMarek Vasut bic r0, #0x0087 4307f4cfcf4SMarek Vasut orr r0, #0x1800 4317f4cfcf4SMarek Vasut orr r0, #0x0005 4327f4cfcf4SMarek Vasut mcr p15, 0, r0, c1, c0, 0 4337f4cfcf4SMarek Vasut CPWAIT r0 4347f4cfcf4SMarek Vasut 4357f4cfcf4SMarek Vasut /* Unlock Icache, Dcache */ 4367f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c1, 1 4377f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 1 4387f4cfcf4SMarek Vasut 4397f4cfcf4SMarek Vasut /* Flush Icache, Dcache, BTB */ 4407f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c7, 0 4417f4cfcf4SMarek Vasut 4427f4cfcf4SMarek Vasut /* Unlock I-TLB, D-TLB */ 4437f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c4, 1 4447f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c8, 1 4457f4cfcf4SMarek Vasut 4467f4cfcf4SMarek Vasut /* Flush TLB */ 4477f4cfcf4SMarek Vasut mcr p15, 0, r0, c8, c7, 0 4487f4cfcf4SMarek Vasut 4497f4cfcf4SMarek Vasut /* Allocate 4096 bytes of Dcache as RAM */ 4507f4cfcf4SMarek Vasut 4517f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4527f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4537f4cfcf4SMarek Vasut 4547f4cfcf4SMarek Vasut mov r4, #0x00 4557f4cfcf4SMarek Vasut mov r5, #0x00 4567f4cfcf4SMarek Vasut mov r2, #0x01 4577f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 0 4587f4cfcf4SMarek Vasut CPWAIT r0 4597f4cfcf4SMarek Vasut 4607f4cfcf4SMarek Vasut /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 4617f4cfcf4SMarek Vasut mov r0, #128 4627f4cfcf4SMarek Vasut ldr r1, =0xfffff000 4637f4cfcf4SMarek Vasut 4647f4cfcf4SMarek Vasutalloc: 4657f4cfcf4SMarek Vasut mcr p15, 0, r1, c7, c2, 5 4667f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4677f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4687f4cfcf4SMarek Vasut strd r4, [r1], #8 4697f4cfcf4SMarek Vasut strd r4, [r1], #8 4707f4cfcf4SMarek Vasut strd r4, [r1], #8 4717f4cfcf4SMarek Vasut strd r4, [r1], #8 4727f4cfcf4SMarek Vasut subs r0, #0x01 4737f4cfcf4SMarek Vasut bne alloc 4747f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4757f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4767f4cfcf4SMarek Vasut mov r2, #0x00 4777f4cfcf4SMarek Vasut mcr p15, 0, r2, c9, c2, 0 4787f4cfcf4SMarek Vasut CPWAIT r0 4797f4cfcf4SMarek Vasut 4807f4cfcf4SMarek Vasut mov pc, lr 4817f4cfcf4SMarek Vasut 4827f4cfcf4SMarek Vasut.section .mmutable, "a" 4837f4cfcf4SMarek Vasutmmutable: 4847f4cfcf4SMarek Vasut .align 14 4857f4cfcf4SMarek Vasut /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 4867f4cfcf4SMarek Vasut .set __base, 0 4877f4cfcf4SMarek Vasut .rept 0xfff 4887f4cfcf4SMarek Vasut .word (__base << 20) | 0xc12 4897f4cfcf4SMarek Vasut .set __base, __base + 1 4907f4cfcf4SMarek Vasut .endr 4917f4cfcf4SMarek Vasut 4927f4cfcf4SMarek Vasut /* 0xfff00000 : 1:1, cached mapping */ 4937f4cfcf4SMarek Vasut .word (0xfff << 20) | 0x1c1e 494abc20abaSMarek Vasut#endif /* CONFIG_CPU_PXA25X */ 495