184ad6884SPeter Tyser/* 220f7b1b7SMarek Vasut * armboot - Startup Code for XScale CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 584ad6884SPeter Tyser * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 684ad6884SPeter Tyser * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 784ad6884SPeter Tyser * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 820f7b1b7SMarek Vasut * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 920f7b1b7SMarek Vasut * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 1020f7b1b7SMarek Vasut * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 1284ad6884SPeter Tyser * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 1320f7b1b7SMarek Vasut * Copyright (C) 2003 Kshitij <kshitij@ti.com> 1420f7b1b7SMarek Vasut * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 1520f7b1b7SMarek Vasut * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 1620f7b1b7SMarek Vasut * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 1720f7b1b7SMarek Vasut * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 1884ad6884SPeter Tyser * 19*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 2084ad6884SPeter Tyser */ 2184ad6884SPeter Tyser 2225ddd1fbSWolfgang Denk#include <asm-offsets.h> 2384ad6884SPeter Tyser#include <config.h> 2484ad6884SPeter Tyser#include <version.h> 257f4cfcf4SMarek Vasut 26abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 277f4cfcf4SMarek Vasut#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 287f4cfcf4SMarek Vasut#error "Init SP address must be set to 0xfffff800 for PXA250" 297f4cfcf4SMarek Vasut#endif 307f4cfcf4SMarek Vasut#endif 317f4cfcf4SMarek Vasut 3284ad6884SPeter Tyser.globl _start 3384ad6884SPeter Tyser_start: b reset 34401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 355ab877b6SMarek Vasut ldr pc, _hang 365ab877b6SMarek Vasut ldr pc, _hang 375ab877b6SMarek Vasut ldr pc, _hang 385ab877b6SMarek Vasut ldr pc, _hang 395ab877b6SMarek Vasut ldr pc, _hang 405ab877b6SMarek Vasut ldr pc, _hang 415ab877b6SMarek Vasut ldr pc, _hang 425ab877b6SMarek Vasut 435ab877b6SMarek Vasut_hang: 445ab877b6SMarek Vasut .word do_hang 455ab877b6SMarek Vasut .word 0x12345678 465ab877b6SMarek Vasut .word 0x12345678 475ab877b6SMarek Vasut .word 0x12345678 485ab877b6SMarek Vasut .word 0x12345678 495ab877b6SMarek Vasut .word 0x12345678 505ab877b6SMarek Vasut .word 0x12345678 515ab877b6SMarek Vasut .word 0x12345678 /* now 16*4=64 */ 525ab877b6SMarek Vasut#else 5384ad6884SPeter Tyser ldr pc, _undefined_instruction 5484ad6884SPeter Tyser ldr pc, _software_interrupt 5584ad6884SPeter Tyser ldr pc, _prefetch_abort 5684ad6884SPeter Tyser ldr pc, _data_abort 5784ad6884SPeter Tyser ldr pc, _not_used 5884ad6884SPeter Tyser ldr pc, _irq 5984ad6884SPeter Tyser ldr pc, _fiq 6084ad6884SPeter Tyser 6184ad6884SPeter Tyser_undefined_instruction: .word undefined_instruction 6284ad6884SPeter Tyser_software_interrupt: .word software_interrupt 6384ad6884SPeter Tyser_prefetch_abort: .word prefetch_abort 6484ad6884SPeter Tyser_data_abort: .word data_abort 6584ad6884SPeter Tyser_not_used: .word not_used 6684ad6884SPeter Tyser_irq: .word irq 6784ad6884SPeter Tyser_fiq: .word fiq 6820f7b1b7SMarek Vasut_pad: .word 0x12345678 /* now 16*4=64 */ 69401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 7020f7b1b7SMarek Vasut.global _end_vect 7120f7b1b7SMarek Vasut_end_vect: 7284ad6884SPeter Tyser 7384ad6884SPeter Tyser .balignl 16,0xdeadbeef 7484ad6884SPeter Tyser/* 7520f7b1b7SMarek Vasut ************************************************************************* 7620f7b1b7SMarek Vasut * 7784ad6884SPeter Tyser * Startup Code (reset vector) 7884ad6884SPeter Tyser * 7920f7b1b7SMarek Vasut * do important init only if we don't start from memory! 8020f7b1b7SMarek Vasut * setup Memory and board specific bits prior to relocation. 8120f7b1b7SMarek Vasut * relocate armboot to ram 8220f7b1b7SMarek Vasut * setup stack 8320f7b1b7SMarek Vasut * 8420f7b1b7SMarek Vasut ************************************************************************* 8584ad6884SPeter Tyser */ 8684ad6884SPeter Tyser 875347f68cSHeiko Schocher.globl _TEXT_BASE 8884ad6884SPeter Tyser_TEXT_BASE: 89508611bcSBenoît Thébaudeau#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 9020f7b1b7SMarek Vasut .word CONFIG_SPL_TEXT_BASE 9120f7b1b7SMarek Vasut#else 9214d0a02aSWolfgang Denk .word CONFIG_SYS_TEXT_BASE 9320f7b1b7SMarek Vasut#endif 9484ad6884SPeter Tyser 9584ad6884SPeter Tyser/* 9684ad6884SPeter Tyser * These are defined in the board-specific linker script. 9720f7b1b7SMarek Vasut * Subtracting _start from them lets the linker put their 9820f7b1b7SMarek Vasut * relative position in the executable instead of leaving 9920f7b1b7SMarek Vasut * them null. 10084ad6884SPeter Tyser */ 1016e96cf9aSMarek Vasut.globl _bss_start_ofs 1026e96cf9aSMarek Vasut_bss_start_ofs: 1036e96cf9aSMarek Vasut .word __bss_start - _start 10484ad6884SPeter Tyser 1056e96cf9aSMarek Vasut.globl _bss_end_ofs 1066e96cf9aSMarek Vasut_bss_end_ofs: 1073929fb0aSSimon Glass .word __bss_end - _start 10884ad6884SPeter Tyser 109f326cbbaSPo-Yu Chuang.globl _end_ofs 110f326cbbaSPo-Yu Chuang_end_ofs: 111f326cbbaSPo-Yu Chuang .word _end - _start 112f326cbbaSPo-Yu Chuang 11384ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 11484ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 11584ad6884SPeter Tyser.globl IRQ_STACK_START 11684ad6884SPeter TyserIRQ_STACK_START: 11784ad6884SPeter Tyser .word 0x0badc0de 11884ad6884SPeter Tyser 11984ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 12084ad6884SPeter Tyser.globl FIQ_STACK_START 12184ad6884SPeter TyserFIQ_STACK_START: 12284ad6884SPeter Tyser .word 0x0badc0de 12320f7b1b7SMarek Vasut#endif 12484ad6884SPeter Tyser 1255347f68cSHeiko Schocher/* IRQ stack memory (calculated at run-time) + 8 bytes */ 1265347f68cSHeiko Schocher.globl IRQ_STACK_START_IN 1275347f68cSHeiko SchocherIRQ_STACK_START_IN: 1285347f68cSHeiko Schocher .word 0x0badc0de 1295347f68cSHeiko Schocher 1305347f68cSHeiko Schocher/* 1315347f68cSHeiko Schocher * the actual reset code 1325347f68cSHeiko Schocher */ 1335347f68cSHeiko Schocher 1345347f68cSHeiko Schocherreset: 1355347f68cSHeiko Schocher /* 1365347f68cSHeiko Schocher * set the cpu to SVC32 mode 1375347f68cSHeiko Schocher */ 1385347f68cSHeiko Schocher mrs r0,cpsr 1395347f68cSHeiko Schocher bic r0,r0,#0x1f 1405347f68cSHeiko Schocher orr r0,r0,#0xd3 1415347f68cSHeiko Schocher msr cpsr,r0 1425347f68cSHeiko Schocher 14320f7b1b7SMarek Vasut#ifndef CONFIG_SKIP_LOWLEVEL_INIT 14420f7b1b7SMarek Vasut bl cpu_init_crit 14520f7b1b7SMarek Vasut#endif 1465347f68cSHeiko Schocher 147abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 1487f4cfcf4SMarek Vasut bl lock_cache_for_stack 1497f4cfcf4SMarek Vasut#endif 1507f4cfcf4SMarek Vasut 151e05e5de7SAlbert ARIBAUD bl _main 1525347f68cSHeiko Schocher 1535347f68cSHeiko Schocher/*------------------------------------------------------------------------------*/ 154e05e5de7SAlbert ARIBAUD 155e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 156e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 157e05e5de7SAlbert ARIBAUD 1583da0e575SAlbert ARIBAUD#ifdef CONFIG_CPU_PXA25X 1593da0e575SAlbert ARIBAUD /* 1603da0e575SAlbert ARIBAUD * Unlock (actually, disable) the cache now that board_init_f 1613da0e575SAlbert ARIBAUD * is done. We could do this earlier but we would need to add 1623da0e575SAlbert ARIBAUD * a new C runtime hook, whereas c_runtime_cpu_setup already 1633da0e575SAlbert ARIBAUD * exists. 1643da0e575SAlbert ARIBAUD * As this routine is just a call to cpu_init_crit, let us 1653da0e575SAlbert ARIBAUD * tail-optimize and do a simple branch here. 1663da0e575SAlbert ARIBAUD */ 1673da0e575SAlbert ARIBAUD b cpu_init_crit 1683da0e575SAlbert ARIBAUD#else 169e05e5de7SAlbert ARIBAUD bx lr 1703da0e575SAlbert ARIBAUD#endif 171e05e5de7SAlbert ARIBAUD 17220f7b1b7SMarek Vasut/* 17320f7b1b7SMarek Vasut ************************************************************************* 17420f7b1b7SMarek Vasut * 17520f7b1b7SMarek Vasut * CPU_init_critical registers 17620f7b1b7SMarek Vasut * 17720f7b1b7SMarek Vasut * setup important registers 17820f7b1b7SMarek Vasut * setup memory timing 17920f7b1b7SMarek Vasut * 18020f7b1b7SMarek Vasut ************************************************************************* 18120f7b1b7SMarek Vasut */ 182abc20abaSMarek Vasut#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 18320f7b1b7SMarek Vasutcpu_init_crit: 18420f7b1b7SMarek Vasut /* 18520f7b1b7SMarek Vasut * flush v4 I/D caches 18620f7b1b7SMarek Vasut */ 18720f7b1b7SMarek Vasut mov r0, #0 18820f7b1b7SMarek Vasut mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 18920f7b1b7SMarek Vasut mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 1902cad92fdSMarek Vasut 19120f7b1b7SMarek Vasut /* 19220f7b1b7SMarek Vasut * disable MMU stuff and caches 19320f7b1b7SMarek Vasut */ 19420f7b1b7SMarek Vasut mrc p15, 0, r0, c1, c0, 0 195097d86d0SMike Dunn bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 19620f7b1b7SMarek Vasut bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 19720f7b1b7SMarek Vasut orr r0, r0, #0x00000002 @ set bit 2 (A) Align 19820f7b1b7SMarek Vasut mcr p15, 0, r0, c1, c0, 0 19984ad6884SPeter Tyser 20020f7b1b7SMarek Vasut mov pc, lr /* back to my caller */ 201abc20abaSMarek Vasut#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 20284ad6884SPeter Tyser 203401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 20420f7b1b7SMarek Vasut/* 20520f7b1b7SMarek Vasut ************************************************************************* 20620f7b1b7SMarek Vasut * 20720f7b1b7SMarek Vasut * Interrupt handling 20820f7b1b7SMarek Vasut * 20920f7b1b7SMarek Vasut ************************************************************************* 21020f7b1b7SMarek Vasut */ 21120f7b1b7SMarek Vasut@ 21220f7b1b7SMarek Vasut@ IRQ stack frame. 21320f7b1b7SMarek Vasut@ 21484ad6884SPeter Tyser#define S_FRAME_SIZE 72 21584ad6884SPeter Tyser 21684ad6884SPeter Tyser#define S_OLD_R0 68 21784ad6884SPeter Tyser#define S_PSR 64 21884ad6884SPeter Tyser#define S_PC 60 21984ad6884SPeter Tyser#define S_LR 56 22084ad6884SPeter Tyser#define S_SP 52 22184ad6884SPeter Tyser 22284ad6884SPeter Tyser#define S_IP 48 22384ad6884SPeter Tyser#define S_FP 44 22484ad6884SPeter Tyser#define S_R10 40 22584ad6884SPeter Tyser#define S_R9 36 22684ad6884SPeter Tyser#define S_R8 32 22784ad6884SPeter Tyser#define S_R7 28 22884ad6884SPeter Tyser#define S_R6 24 22984ad6884SPeter Tyser#define S_R5 20 23084ad6884SPeter Tyser#define S_R4 16 23184ad6884SPeter Tyser#define S_R3 12 23284ad6884SPeter Tyser#define S_R2 8 23384ad6884SPeter Tyser#define S_R1 4 23484ad6884SPeter Tyser#define S_R0 0 23584ad6884SPeter Tyser 23684ad6884SPeter Tyser#define MODE_SVC 0x13 23720f7b1b7SMarek Vasut#define I_BIT 0x80 23884ad6884SPeter Tyser 23920f7b1b7SMarek Vasut/* 24020f7b1b7SMarek Vasut * use bad_save_user_regs for abort/prefetch/undef/swi ... 24120f7b1b7SMarek Vasut * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 24220f7b1b7SMarek Vasut */ 24384ad6884SPeter Tyser 24484ad6884SPeter Tyser .macro bad_save_user_regs 24520f7b1b7SMarek Vasut sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 24620f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 24784ad6884SPeter Tyser 24820f7b1b7SMarek Vasut ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 24920f7b1b7SMarek Vasut ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 25020f7b1b7SMarek Vasut add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 25184ad6884SPeter Tyser 25284ad6884SPeter Tyser add r5, sp, #S_SP 25384ad6884SPeter Tyser mov r1, lr 25420f7b1b7SMarek Vasut stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 25520f7b1b7SMarek Vasut mov r0, sp @ save current stack into r0 (param register) 25684ad6884SPeter Tyser .endm 25784ad6884SPeter Tyser 25884ad6884SPeter Tyser .macro irq_save_user_regs 25984ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 26020f7b1b7SMarek Vasut stmia sp, {r0 - r12} @ Calling r0-r12 26120f7b1b7SMarek Vasut add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 26220f7b1b7SMarek Vasut stmdb r8, {sp, lr}^ @ Calling SP, LR 26320f7b1b7SMarek Vasut str lr, [r8, #0] @ Save calling PC 26484ad6884SPeter Tyser mrs r6, spsr 26520f7b1b7SMarek Vasut str r6, [r8, #4] @ Save CPSR 26620f7b1b7SMarek Vasut str r0, [r8, #8] @ Save OLD_R0 26784ad6884SPeter Tyser mov r0, sp 26884ad6884SPeter Tyser .endm 26984ad6884SPeter Tyser 27084ad6884SPeter Tyser .macro irq_restore_user_regs 27184ad6884SPeter Tyser ldmia sp, {r0 - lr}^ @ Calling r0 - lr 27284ad6884SPeter Tyser mov r0, r0 27384ad6884SPeter Tyser ldr lr, [sp, #S_PC] @ Get PC 27484ad6884SPeter Tyser add sp, sp, #S_FRAME_SIZE 27584ad6884SPeter Tyser subs pc, lr, #4 @ return & move spsr_svc into cpsr 27684ad6884SPeter Tyser .endm 27784ad6884SPeter Tyser 27884ad6884SPeter Tyser .macro get_bad_stack 27920f7b1b7SMarek Vasut ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 28084ad6884SPeter Tyser 28120f7b1b7SMarek Vasut str lr, [r13] @ save caller lr in position 0 of saved stack 28220f7b1b7SMarek Vasut mrs lr, spsr @ get the spsr 28320f7b1b7SMarek Vasut str lr, [r13, #4] @ save spsr in position 1 of saved stack 28484ad6884SPeter Tyser 28584ad6884SPeter Tyser mov r13, #MODE_SVC @ prepare SVC-Mode 28620f7b1b7SMarek Vasut @ msr spsr_c, r13 28720f7b1b7SMarek Vasut msr spsr, r13 @ switch modes, make sure moves will execute 28820f7b1b7SMarek Vasut mov lr, pc @ capture return pc 28920f7b1b7SMarek Vasut movs pc, lr @ jump to next instruction & switch modes. 29020f7b1b7SMarek Vasut .endm 29120f7b1b7SMarek Vasut 29220f7b1b7SMarek Vasut .macro get_bad_stack_swi 29320f7b1b7SMarek Vasut sub r13, r13, #4 @ space on current stack for scratch reg. 29420f7b1b7SMarek Vasut str r0, [r13] @ save R0's value. 29520f7b1b7SMarek Vasut ldr r0, IRQ_STACK_START_IN @ get data regions start 29620f7b1b7SMarek Vasut str lr, [r0] @ save caller lr in position 0 of saved stack 2974411b2aeSTetsuyuki Kobayashi mrs lr, spsr @ get the spsr 29820f7b1b7SMarek Vasut str lr, [r0, #4] @ save spsr in position 1 of saved stack 2994411b2aeSTetsuyuki Kobayashi ldr lr, [r0] @ restore lr 30020f7b1b7SMarek Vasut ldr r0, [r13] @ restore r0 30120f7b1b7SMarek Vasut add r13, r13, #4 @ pop stack entry 30284ad6884SPeter Tyser .endm 30384ad6884SPeter Tyser 30484ad6884SPeter Tyser .macro get_irq_stack @ setup IRQ stack 30584ad6884SPeter Tyser ldr sp, IRQ_STACK_START 30684ad6884SPeter Tyser .endm 30784ad6884SPeter Tyser 30884ad6884SPeter Tyser .macro get_fiq_stack @ setup FIQ stack 30984ad6884SPeter Tyser ldr sp, FIQ_STACK_START 31084ad6884SPeter Tyser .endm 31120f7b1b7SMarek Vasut#endif /* CONFIG_SPL_BUILD */ 31284ad6884SPeter Tyser 31320f7b1b7SMarek Vasut/* 31420f7b1b7SMarek Vasut * exception handlers 31520f7b1b7SMarek Vasut */ 316401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 3175ab877b6SMarek Vasut .align 5 3185ab877b6SMarek Vasutdo_hang: 31920f7b1b7SMarek Vasut ldr sp, _TEXT_BASE /* use 32 words about stack */ 3205ab877b6SMarek Vasut bl hang /* hang and never return */ 32120f7b1b7SMarek Vasut#else /* !CONFIG_SPL_BUILD */ 32284ad6884SPeter Tyser .align 5 32384ad6884SPeter Tyserundefined_instruction: 32484ad6884SPeter Tyser get_bad_stack 32584ad6884SPeter Tyser bad_save_user_regs 32684ad6884SPeter Tyser bl do_undefined_instruction 32784ad6884SPeter Tyser 32884ad6884SPeter Tyser .align 5 32984ad6884SPeter Tysersoftware_interrupt: 33020f7b1b7SMarek Vasut get_bad_stack_swi 33184ad6884SPeter Tyser bad_save_user_regs 33284ad6884SPeter Tyser bl do_software_interrupt 33384ad6884SPeter Tyser 33484ad6884SPeter Tyser .align 5 33584ad6884SPeter Tyserprefetch_abort: 33684ad6884SPeter Tyser get_bad_stack 33784ad6884SPeter Tyser bad_save_user_regs 33884ad6884SPeter Tyser bl do_prefetch_abort 33984ad6884SPeter Tyser 34084ad6884SPeter Tyser .align 5 34184ad6884SPeter Tyserdata_abort: 34284ad6884SPeter Tyser get_bad_stack 34384ad6884SPeter Tyser bad_save_user_regs 34484ad6884SPeter Tyser bl do_data_abort 34584ad6884SPeter Tyser 34684ad6884SPeter Tyser .align 5 34784ad6884SPeter Tysernot_used: 34884ad6884SPeter Tyser get_bad_stack 34984ad6884SPeter Tyser bad_save_user_regs 35084ad6884SPeter Tyser bl do_not_used 35184ad6884SPeter Tyser 35284ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 35384ad6884SPeter Tyser 35484ad6884SPeter Tyser .align 5 35584ad6884SPeter Tyserirq: 35684ad6884SPeter Tyser get_irq_stack 35784ad6884SPeter Tyser irq_save_user_regs 35884ad6884SPeter Tyser bl do_irq 35984ad6884SPeter Tyser irq_restore_user_regs 36084ad6884SPeter Tyser 36184ad6884SPeter Tyser .align 5 36284ad6884SPeter Tyserfiq: 36384ad6884SPeter Tyser get_fiq_stack 36420f7b1b7SMarek Vasut /* someone ought to write a more effiction fiq_save_user_regs */ 36520f7b1b7SMarek Vasut irq_save_user_regs 36620f7b1b7SMarek Vasut bl do_fiq 36784ad6884SPeter Tyser irq_restore_user_regs 36884ad6884SPeter Tyser 36920f7b1b7SMarek Vasut#else 37084ad6884SPeter Tyser 37184ad6884SPeter Tyser .align 5 37284ad6884SPeter Tyserirq: 37384ad6884SPeter Tyser get_bad_stack 37484ad6884SPeter Tyser bad_save_user_regs 37584ad6884SPeter Tyser bl do_irq 37684ad6884SPeter Tyser 37784ad6884SPeter Tyser .align 5 37884ad6884SPeter Tyserfiq: 37984ad6884SPeter Tyser get_bad_stack 38084ad6884SPeter Tyser bad_save_user_regs 38184ad6884SPeter Tyser bl do_fiq 38284ad6884SPeter Tyser 38320f7b1b7SMarek Vasut#endif 38484ad6884SPeter Tyser .align 5 385401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 3867f4cfcf4SMarek Vasut 3877f4cfcf4SMarek Vasut 3887f4cfcf4SMarek Vasut/* 3897f4cfcf4SMarek Vasut * Enable MMU to use DCache as DRAM. 3907f4cfcf4SMarek Vasut * 3917f4cfcf4SMarek Vasut * This is useful on PXA25x and PXA26x in early bootstages, where there is no 3927f4cfcf4SMarek Vasut * other possible memory available to hold stack. 3937f4cfcf4SMarek Vasut */ 394abc20abaSMarek Vasut#ifdef CONFIG_CPU_PXA25X 3957f4cfcf4SMarek Vasut.macro CPWAIT reg 3967f4cfcf4SMarek Vasut mrc p15, 0, \reg, c2, c0, 0 3977f4cfcf4SMarek Vasut mov \reg, \reg 3987f4cfcf4SMarek Vasut sub pc, pc, #4 3997f4cfcf4SMarek Vasut.endm 4007f4cfcf4SMarek Vasutlock_cache_for_stack: 4017f4cfcf4SMarek Vasut /* Domain access -- enable for all CPs */ 4027f4cfcf4SMarek Vasut ldr r0, =0x0000ffff 4037f4cfcf4SMarek Vasut mcr p15, 0, r0, c3, c0, 0 4047f4cfcf4SMarek Vasut 4057f4cfcf4SMarek Vasut /* Point TTBR to MMU table */ 4067f4cfcf4SMarek Vasut ldr r0, =mmutable 4077f4cfcf4SMarek Vasut mcr p15, 0, r0, c2, c0, 0 4087f4cfcf4SMarek Vasut 4097f4cfcf4SMarek Vasut /* Kick in MMU, ICache, DCache, BTB */ 4107f4cfcf4SMarek Vasut mrc p15, 0, r0, c1, c0, 0 4117f4cfcf4SMarek Vasut bic r0, #0x1b00 4127f4cfcf4SMarek Vasut bic r0, #0x0087 4137f4cfcf4SMarek Vasut orr r0, #0x1800 4147f4cfcf4SMarek Vasut orr r0, #0x0005 4157f4cfcf4SMarek Vasut mcr p15, 0, r0, c1, c0, 0 4167f4cfcf4SMarek Vasut CPWAIT r0 4177f4cfcf4SMarek Vasut 4187f4cfcf4SMarek Vasut /* Unlock Icache, Dcache */ 4197f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c1, 1 4207f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 1 4217f4cfcf4SMarek Vasut 4227f4cfcf4SMarek Vasut /* Flush Icache, Dcache, BTB */ 4237f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c7, 0 4247f4cfcf4SMarek Vasut 4257f4cfcf4SMarek Vasut /* Unlock I-TLB, D-TLB */ 4267f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c4, 1 4277f4cfcf4SMarek Vasut mcr p15, 0, r0, c10, c8, 1 4287f4cfcf4SMarek Vasut 4297f4cfcf4SMarek Vasut /* Flush TLB */ 4307f4cfcf4SMarek Vasut mcr p15, 0, r0, c8, c7, 0 4317f4cfcf4SMarek Vasut 4327f4cfcf4SMarek Vasut /* Allocate 4096 bytes of Dcache as RAM */ 4337f4cfcf4SMarek Vasut 4347f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4357f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4367f4cfcf4SMarek Vasut 4377f4cfcf4SMarek Vasut mov r4, #0x00 4387f4cfcf4SMarek Vasut mov r5, #0x00 4397f4cfcf4SMarek Vasut mov r2, #0x01 4407f4cfcf4SMarek Vasut mcr p15, 0, r0, c9, c2, 0 4417f4cfcf4SMarek Vasut CPWAIT r0 4427f4cfcf4SMarek Vasut 4437f4cfcf4SMarek Vasut /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 4447f4cfcf4SMarek Vasut mov r0, #128 4457f4cfcf4SMarek Vasut ldr r1, =0xfffff000 4467f4cfcf4SMarek Vasut 4477f4cfcf4SMarek Vasutalloc: 4487f4cfcf4SMarek Vasut mcr p15, 0, r1, c7, c2, 5 4497f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4507f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4517f4cfcf4SMarek Vasut strd r4, [r1], #8 4527f4cfcf4SMarek Vasut strd r4, [r1], #8 4537f4cfcf4SMarek Vasut strd r4, [r1], #8 4547f4cfcf4SMarek Vasut strd r4, [r1], #8 4557f4cfcf4SMarek Vasut subs r0, #0x01 4567f4cfcf4SMarek Vasut bne alloc 4577f4cfcf4SMarek Vasut /* Drain pending loads and stores */ 4587f4cfcf4SMarek Vasut mcr p15, 0, r0, c7, c10, 4 4597f4cfcf4SMarek Vasut mov r2, #0x00 4607f4cfcf4SMarek Vasut mcr p15, 0, r2, c9, c2, 0 4617f4cfcf4SMarek Vasut CPWAIT r0 4627f4cfcf4SMarek Vasut 4637f4cfcf4SMarek Vasut mov pc, lr 4647f4cfcf4SMarek Vasut 4657f4cfcf4SMarek Vasut.section .mmutable, "a" 4667f4cfcf4SMarek Vasutmmutable: 4677f4cfcf4SMarek Vasut .align 14 4687f4cfcf4SMarek Vasut /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 4697f4cfcf4SMarek Vasut .set __base, 0 4707f4cfcf4SMarek Vasut .rept 0xfff 4717f4cfcf4SMarek Vasut .word (__base << 20) | 0xc12 4727f4cfcf4SMarek Vasut .set __base, __base + 1 4737f4cfcf4SMarek Vasut .endr 4747f4cfcf4SMarek Vasut 4757f4cfcf4SMarek Vasut /* 0xfff00000 : 1:1, cached mapping */ 4767f4cfcf4SMarek Vasut .word (0xfff << 20) | 0x1c1e 477abc20abaSMarek Vasut#endif /* CONFIG_CPU_PXA25X */ 478