xref: /openbmc/u-boot/arch/arm/cpu/pxa/cache.c (revision 8ee59472)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
4  */
5 
6 #include <linux/types.h>
7 #include <common.h>
8 
9 #ifndef CONFIG_SYS_DCACHE_OFF
10 void invalidate_dcache_all(void)
11 {
12 	/* Flush/Invalidate I cache */
13 	asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
14 	/* Flush/Invalidate D cache */
15 	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
16 }
17 
18 void flush_dcache_all(void)
19 {
20 	return invalidate_dcache_all();
21 }
22 
23 void invalidate_dcache_range(unsigned long start, unsigned long stop)
24 {
25 	start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
26 	stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
27 
28 	while (start <= stop) {
29 		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
30 		start += CONFIG_SYS_CACHELINE_SIZE;
31 	}
32 }
33 
34 void flush_dcache_range(unsigned long start, unsigned long stop)
35 {
36 	return invalidate_dcache_range(start, stop);
37 }
38 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
39 void invalidate_dcache_all(void)
40 {
41 }
42 
43 void flush_dcache_all(void)
44 {
45 }
46 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
47 
48 /*
49  * Stub implementations for l2 cache operations
50  */
51 
52 __weak void l2_cache_disable(void) {}
53 
54 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
55 __weak void invalidate_l2_cache(void) {}
56 #endif
57