xref: /openbmc/u-boot/arch/arm/cpu/pxa/cache.c (revision 0649cd0d)
1 /*
2  * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <linux/types.h>
8 #include <common.h>
9 
10 #ifndef CONFIG_SYS_DCACHE_OFF
11 void invalidate_dcache_all(void)
12 {
13 	/* Flush/Invalidate I cache */
14 	asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
15 	/* Flush/Invalidate D cache */
16 	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
17 }
18 
19 void flush_dcache_all(void)
20 {
21 	return invalidate_dcache_all();
22 }
23 
24 void invalidate_dcache_range(unsigned long start, unsigned long stop)
25 {
26 	start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
27 	stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
28 
29 	while (start <= stop) {
30 		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
31 		start += CONFIG_SYS_CACHELINE_SIZE;
32 	}
33 }
34 
35 void flush_dcache_range(unsigned long start, unsigned long stop)
36 {
37 	return invalidate_dcache_range(start, stop);
38 }
39 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
40 void invalidate_dcache_all(void)
41 {
42 }
43 
44 void flush_dcache_all(void)
45 {
46 }
47 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
48 
49 /*
50  * Stub implementations for l2 cache operations
51  */
52 
53 __weak void l2_cache_disable(void) {}
54 
55 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
56 __weak void invalidate_l2_cache(void) {}
57 #endif
58