xref: /openbmc/u-boot/arch/arm/cpu/armv8/transition.S (revision c4b45009)
1/*
2 * (C) Copyright 2013
3 * David Feng <fenghua@phytium.com.cn>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7
8#include <asm-offsets.h>
9#include <config.h>
10#include <version.h>
11#include <linux/linkage.h>
12#include <asm/macro.h>
13
14ENTRY(armv8_switch_to_el2)
15	switch_el x0, 1f, 0f, 0f
160:	ret
171:
18	mov	x0, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
19	msr	scr_el3, x0
20	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
21	mov	x0, #0x33ff
22	msr	cptr_el2, x0	/* Disable coprocessor traps to EL2 */
23
24	/* Initialize SCTLR_EL2 */
25	msr	sctlr_el2, xzr
26
27	/* Return to the EL2_SP2 mode from EL3 */
28	mov	x0, sp
29	msr	sp_el2, x0	/* Migrate SP */
30	mrs	x0, vbar_el3
31	msr	vbar_el2, x0	/* Migrate VBAR */
32	mov	x0, #0x3c9
33	msr	spsr_el3, x0	/* EL2_SP2 | D | A | I | F */
34	msr	elr_el3, lr
35	eret
36ENDPROC(armv8_switch_to_el2)
37
38ENTRY(armv8_switch_to_el1)
39	switch_el x0, 0f, 1f, 0f
400:	ret
411:
42	/* Initialize Generic Timers */
43	mrs	x0, cnthctl_el2
44	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
45	msr	cnthctl_el2, x0
46	msr	cntvoff_el2, xzr
47	mrs	x0, cntkctl_el1
48	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
49	msr	cntkctl_el1, x0
50
51	/* Initilize MPID/MPIDR registers */
52	mrs	x0, midr_el1
53	mrs	x1, mpidr_el1
54	msr	vpidr_el2, x0
55	msr	vmpidr_el2, x1
56
57	/* Disable coprocessor traps */
58	mov	x0, #0x33ff
59	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
60	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
61	mov	x0, #3 << 20
62	msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
63
64	/* Initialize HCR_EL2 */
65	mov	x0, #(1 << 31)		/* 64bit EL1 */
66	orr	x0, x0, #(1 << 29)	/* Disable HVC */
67	msr	hcr_el2, x0
68
69	/* SCTLR_EL1 initialization */
70	mov	x0, #0x0800
71	movk	x0, #0x30d0, lsl #16
72	msr	sctlr_el1, x0
73
74	/* Return to the EL1_SP1 mode from EL2 */
75	mov	x0, sp
76	msr	sp_el1, x0		/* Migrate SP */
77	mrs	x0, vbar_el2
78	msr	vbar_el1, x0		/* Migrate VBAR */
79	mov	x0, #0x3c5
80	msr	spsr_el2, x0		/* EL1_SP1 | D | A | I | F */
81	msr	elr_el2, lr
82	eret
83ENDPROC(armv8_switch_to_el1)
84