1/* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <asm-offsets.h> 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/macro.h> 12#include <asm/armv8/mmu.h> 13 14/************************************************************************* 15 * 16 * Startup Code (reset vector) 17 * 18 *************************************************************************/ 19 20.globl _start 21_start: 22 b reset 23 24 .align 3 25 26.globl _TEXT_BASE 27_TEXT_BASE: 28 .quad CONFIG_SYS_TEXT_BASE 29 30/* 31 * These are defined in the linker script. 32 */ 33.globl _end_ofs 34_end_ofs: 35 .quad _end - _start 36 37.globl _bss_start_ofs 38_bss_start_ofs: 39 .quad __bss_start - _start 40 41.globl _bss_end_ofs 42_bss_end_ofs: 43 .quad __bss_end - _start 44 45reset: 46#ifdef CONFIG_SYS_RESET_SCTRL 47 bl reset_sctrl 48#endif 49 /* 50 * Could be EL3/EL2/EL1, Initial State: 51 * Little Endian, MMU Disabled, i/dCache Disabled 52 */ 53 adr x0, vectors 54 switch_el x1, 3f, 2f, 1f 553: msr vbar_el3, x0 56 mrs x0, scr_el3 57 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ 58 msr scr_el3, x0 59 msr cptr_el3, xzr /* Enable FP/SIMD */ 60#ifdef COUNTER_FREQUENCY 61 ldr x0, =COUNTER_FREQUENCY 62 msr cntfrq_el0, x0 /* Initialize CNTFRQ */ 63#endif 64 b 0f 652: msr vbar_el2, x0 66 mov x0, #0x33ff 67 msr cptr_el2, x0 /* Enable FP/SIMD */ 68 b 0f 691: msr vbar_el1, x0 70 mov x0, #3 << 20 71 msr cpacr_el1, x0 /* Enable FP/SIMD */ 720: 73 74 /* Apply ARM core specific erratas */ 75 bl apply_core_errata 76 77 /* 78 * Cache/BPB/TLB Invalidate 79 * i-cache is invalidated before enabled in icache_enable() 80 * tlb is invalidated before mmu is enabled in dcache_enable() 81 * d-cache is invalidated before enabled in dcache_enable() 82 */ 83 84 /* Processor specific initialization */ 85 bl lowlevel_init 86 87#ifdef CONFIG_ARMV8_MULTIENTRY 88 branch_if_master x0, x1, master_cpu 89 90 /* 91 * Slave CPUs 92 */ 93slave_cpu: 94 wfe 95 ldr x1, =CPU_RELEASE_ADDR 96 ldr x0, [x1] 97 cbz x0, slave_cpu 98 br x0 /* branch to the given address */ 99master_cpu: 100 /* On the master CPU */ 101#endif /* CONFIG_ARMV8_MULTIENTRY */ 102 103 bl _main 104 105#ifdef CONFIG_SYS_RESET_SCTRL 106reset_sctrl: 107 switch_el x1, 3f, 2f, 1f 1083: 109 mrs x0, sctlr_el3 110 b 0f 1112: 112 mrs x0, sctlr_el2 113 b 0f 1141: 115 mrs x0, sctlr_el1 116 1170: 118 ldr x1, =0xfdfffffa 119 and x0, x0, x1 120 121 switch_el x1, 6f, 5f, 4f 1226: 123 msr sctlr_el3, x0 124 b 7f 1255: 126 msr sctlr_el2, x0 127 b 7f 1284: 129 msr sctlr_el1, x0 130 1317: 132 dsb sy 133 isb 134 b __asm_invalidate_tlb_all 135 ret 136#endif 137 138/*-----------------------------------------------------------------------*/ 139 140WEAK(apply_core_errata) 141 142 mov x29, lr /* Save LR */ 143 /* For now, we support Cortex-A57 specific errata only */ 144 145 /* Check if we are running on a Cortex-A57 core */ 146 branch_if_a57_core x0, apply_a57_core_errata 1470: 148 mov lr, x29 /* Restore LR */ 149 ret 150 151apply_a57_core_errata: 152 153#ifdef CONFIG_ARM_ERRATA_828024 154 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 155 /* Disable non-allocate hint of w-b-n-a memory type */ 156 orr x0, x0, #1 << 49 157 /* Disable write streaming no L1-allocate threshold */ 158 orr x0, x0, #3 << 25 159 /* Disable write streaming no-allocate threshold */ 160 orr x0, x0, #3 << 27 161 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 162#endif 163 164#ifdef CONFIG_ARM_ERRATA_826974 165 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 166 /* Disable speculative load execution ahead of a DMB */ 167 orr x0, x0, #1 << 59 168 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 169#endif 170 171#ifdef CONFIG_ARM_ERRATA_833471 172 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 173 /* FPSCR write flush. 174 * Note that in some cases where a flush is unnecessary this 175 could impact performance. */ 176 orr x0, x0, #1 << 38 177 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 178#endif 179 180#ifdef CONFIG_ARM_ERRATA_829520 181 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 182 /* Disable Indirect Predictor bit will prevent this erratum 183 from occurring 184 * Note that in some cases where a flush is unnecessary this 185 could impact performance. */ 186 orr x0, x0, #1 << 4 187 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 188#endif 189 190#ifdef CONFIG_ARM_ERRATA_833069 191 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 192 /* Disable Enable Invalidates of BTB bit */ 193 and x0, x0, #0xE 194 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 195#endif 196 b 0b 197ENDPROC(apply_core_errata) 198 199/*-----------------------------------------------------------------------*/ 200 201WEAK(lowlevel_init) 202 mov x29, lr /* Save LR */ 203 204#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 205 branch_if_slave x0, 1f 206 ldr x0, =GICD_BASE 207 bl gic_init_secure 2081: 209#if defined(CONFIG_GICV3) 210 ldr x0, =GICR_BASE 211 bl gic_init_secure_percpu 212#elif defined(CONFIG_GICV2) 213 ldr x0, =GICD_BASE 214 ldr x1, =GICC_BASE 215 bl gic_init_secure_percpu 216#endif 217#endif 218 219#ifdef CONFIG_ARMV8_MULTIENTRY 220 branch_if_master x0, x1, 2f 221 222 /* 223 * Slave should wait for master clearing spin table. 224 * This sync prevent salves observing incorrect 225 * value of spin table and jumping to wrong place. 226 */ 227#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 228#ifdef CONFIG_GICV2 229 ldr x0, =GICC_BASE 230#endif 231 bl gic_wait_for_interrupt 232#endif 233 234 /* 235 * All slaves will enter EL2 and optionally EL1. 236 */ 237 bl armv8_switch_to_el2 238#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 239 bl armv8_switch_to_el1 240#endif 241 242#endif /* CONFIG_ARMV8_MULTIENTRY */ 243 2442: 245 mov lr, x29 /* Restore LR */ 246 ret 247ENDPROC(lowlevel_init) 248 249WEAK(smp_kick_all_cpus) 250 /* Kick secondary cpus up by SGI 0 interrupt */ 251 mov x29, lr /* Save LR */ 252#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 253 ldr x0, =GICD_BASE 254 bl gic_kick_secondary_cpus 255#endif 256 mov lr, x29 /* Restore LR */ 257 ret 258ENDPROC(smp_kick_all_cpus) 259 260/*-----------------------------------------------------------------------*/ 261 262ENTRY(c_runtime_cpu_setup) 263 /* Relocate vBAR */ 264 adr x0, vectors 265 switch_el x1, 3f, 2f, 1f 2663: msr vbar_el3, x0 267 b 0f 2682: msr vbar_el2, x0 269 b 0f 2701: msr vbar_el1, x0 2710: 272 273 ret 274ENDPROC(c_runtime_cpu_setup) 275