1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <fsl_ifc.h> 11 #include <i2c.h> 12 #include <fsl_csu.h> 13 #include <asm/arch/fdt.h> 14 #include <asm/arch/ppa.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 u32 spl_boot_device(void) 19 { 20 #ifdef CONFIG_SPL_MMC_SUPPORT 21 return BOOT_DEVICE_MMC1; 22 #endif 23 #ifdef CONFIG_SPL_NAND_SUPPORT 24 return BOOT_DEVICE_NAND; 25 #endif 26 return 0; 27 } 28 29 u32 spl_boot_mode(const u32 boot_device) 30 { 31 switch (spl_boot_device()) { 32 case BOOT_DEVICE_MMC1: 33 #ifdef CONFIG_SPL_FAT_SUPPORT 34 return MMCSD_MODE_FS; 35 #else 36 return MMCSD_MODE_RAW; 37 #endif 38 case BOOT_DEVICE_NAND: 39 return 0; 40 default: 41 puts("spl: error: unsupported device\n"); 42 hang(); 43 } 44 } 45 46 #ifdef CONFIG_SPL_BUILD 47 48 void spl_board_init(void) 49 { 50 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) 51 /* 52 * In case of Secure Boot, the IBR configures the SMMU 53 * to allow only Secure transactions. 54 * SMMU must be reset in bypass mode. 55 * Set the ClientPD bit and Clear the USFCFG Bit 56 */ 57 u32 val; 58 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 59 out_le32(SMMU_SCR0, val); 60 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 61 out_le32(SMMU_NSCR0, val); 62 #endif 63 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 64 enable_layerscape_ns_access(); 65 #endif 66 #ifdef CONFIG_SPL_FSL_LS_PPA 67 ppa_init(); 68 #endif 69 } 70 71 void board_init_f(ulong dummy) 72 { 73 /* Clear global data */ 74 memset((void *)gd, 0, sizeof(gd_t)); 75 board_early_init_f(); 76 timer_init(); 77 #ifdef CONFIG_ARCH_LS2080A 78 env_init(); 79 #endif 80 get_clocks(); 81 82 preloader_console_init(); 83 84 #ifdef CONFIG_SPL_I2C_SUPPORT 85 i2c_init_all(); 86 #endif 87 dram_init(); 88 #ifdef CONFIG_SPL_FSL_LS_PPA 89 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE 90 #error Need secure RAM for PPA 91 #endif 92 /* 93 * Secure memory location is determined in dram_init_banksize(). 94 * gd->ram_size is deducted by the size of secure ram. 95 */ 96 dram_init_banksize(); 97 98 /* 99 * After dram_init_bank_size(), we know U-Boot only uses the first 100 * memory bank regardless how big the memory is. 101 */ 102 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 103 104 /* 105 * If PPA is loaded, U-Boot will resume running at EL2. 106 * Cache and MMU will be enabled. Need a place for TLB. 107 * U-Boot will be relocated to the end of available memory 108 * in first bank. At this point, we cannot know how much 109 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK 110 * to avoid overlapping. As soon as the RAM version U-Boot sets 111 * up new MMU, this space is no longer needed. 112 */ 113 gd->ram_top -= SPL_TLB_SETBACK; 114 gd->arch.tlb_size = PGTABLE_SIZE; 115 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); 116 gd->arch.tlb_allocated = gd->arch.tlb_addr; 117 #endif /* CONFIG_SPL_FSL_LS_PPA */ 118 } 119 #endif /* CONFIG_SPL_BUILD */ 120