1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <fsl_ifc.h> 10 #include <i2c.h> 11 #include <fsl_csu.h> 12 #include <asm/arch/fdt.h> 13 #include <asm/arch/ppa.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 u32 spl_boot_device(void) 18 { 19 #ifdef CONFIG_SPL_MMC_SUPPORT 20 return BOOT_DEVICE_MMC1; 21 #endif 22 #ifdef CONFIG_SPL_NAND_SUPPORT 23 return BOOT_DEVICE_NAND; 24 #endif 25 return 0; 26 } 27 28 #ifdef CONFIG_SPL_BUILD 29 30 void spl_board_init(void) 31 { 32 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) 33 /* 34 * In case of Secure Boot, the IBR configures the SMMU 35 * to allow only Secure transactions. 36 * SMMU must be reset in bypass mode. 37 * Set the ClientPD bit and Clear the USFCFG Bit 38 */ 39 u32 val; 40 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 41 out_le32(SMMU_SCR0, val); 42 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 43 out_le32(SMMU_NSCR0, val); 44 #endif 45 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 46 enable_layerscape_ns_access(); 47 #endif 48 #ifdef CONFIG_SPL_FSL_LS_PPA 49 ppa_init(); 50 #endif 51 } 52 53 void board_init_f(ulong dummy) 54 { 55 /* Clear global data */ 56 memset((void *)gd, 0, sizeof(gd_t)); 57 board_early_init_f(); 58 timer_init(); 59 #ifdef CONFIG_ARCH_LS2080A 60 env_init(); 61 #endif 62 get_clocks(); 63 64 preloader_console_init(); 65 spl_set_bd(); 66 67 #ifdef CONFIG_SPL_I2C_SUPPORT 68 i2c_init_all(); 69 #endif 70 #ifdef CONFIG_VID 71 init_func_vid(); 72 #endif 73 dram_init(); 74 #ifdef CONFIG_SPL_FSL_LS_PPA 75 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE 76 #error Need secure RAM for PPA 77 #endif 78 /* 79 * Secure memory location is determined in dram_init_banksize(). 80 * gd->ram_size is deducted by the size of secure ram. 81 */ 82 dram_init_banksize(); 83 84 /* 85 * After dram_init_bank_size(), we know U-Boot only uses the first 86 * memory bank regardless how big the memory is. 87 */ 88 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 89 90 /* 91 * If PPA is loaded, U-Boot will resume running at EL2. 92 * Cache and MMU will be enabled. Need a place for TLB. 93 * U-Boot will be relocated to the end of available memory 94 * in first bank. At this point, we cannot know how much 95 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK 96 * to avoid overlapping. As soon as the RAM version U-Boot sets 97 * up new MMU, this space is no longer needed. 98 */ 99 gd->ram_top -= SPL_TLB_SETBACK; 100 gd->arch.tlb_size = PGTABLE_SIZE; 101 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); 102 gd->arch.tlb_allocated = gd->arch.tlb_addr; 103 #endif /* CONFIG_SPL_FSL_LS_PPA */ 104 } 105 106 #ifdef CONFIG_SPL_OS_BOOT 107 /* 108 * Return 109 * 0 if booting into OS is selected 110 * 1 if booting into U-Boot is selected 111 */ 112 int spl_start_uboot(void) 113 { 114 env_init(); 115 if (env_get_yesno("boot_os") != 0) 116 return 0; 117 118 return 1; 119 } 120 #endif /* CONFIG_SPL_OS_BOOT */ 121 #ifdef CONFIG_SPL_LOAD_FIT 122 int board_fit_config_name_match(const char *name) 123 { 124 /* Just empty function now - can't decide what to choose */ 125 debug("%s: %s\n", __func__, name); 126 127 return 0; 128 } 129 #endif 130 #endif /* CONFIG_SPL_BUILD */ 131