1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <fsl_ifc.h> 11 #include <i2c.h> 12 #include <fsl_csu.h> 13 #include <asm/arch/fdt.h> 14 #include <asm/arch/ppa.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 u32 spl_boot_device(void) 19 { 20 #ifdef CONFIG_SPL_MMC_SUPPORT 21 return BOOT_DEVICE_MMC1; 22 #endif 23 #ifdef CONFIG_SPL_NAND_SUPPORT 24 return BOOT_DEVICE_NAND; 25 #endif 26 return 0; 27 } 28 29 #ifdef CONFIG_SPL_BUILD 30 31 void spl_board_init(void) 32 { 33 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) 34 /* 35 * In case of Secure Boot, the IBR configures the SMMU 36 * to allow only Secure transactions. 37 * SMMU must be reset in bypass mode. 38 * Set the ClientPD bit and Clear the USFCFG Bit 39 */ 40 u32 val; 41 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 42 out_le32(SMMU_SCR0, val); 43 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 44 out_le32(SMMU_NSCR0, val); 45 #endif 46 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 47 enable_layerscape_ns_access(); 48 #endif 49 #ifdef CONFIG_SPL_FSL_LS_PPA 50 ppa_init(); 51 #endif 52 } 53 54 void board_init_f(ulong dummy) 55 { 56 /* Clear global data */ 57 memset((void *)gd, 0, sizeof(gd_t)); 58 board_early_init_f(); 59 timer_init(); 60 #ifdef CONFIG_ARCH_LS2080A 61 env_init(); 62 #endif 63 get_clocks(); 64 65 preloader_console_init(); 66 spl_set_bd(); 67 68 #ifdef CONFIG_SPL_I2C_SUPPORT 69 i2c_init_all(); 70 #endif 71 #ifdef CONFIG_VID 72 init_func_vid(); 73 #endif 74 dram_init(); 75 #ifdef CONFIG_SPL_FSL_LS_PPA 76 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE 77 #error Need secure RAM for PPA 78 #endif 79 /* 80 * Secure memory location is determined in dram_init_banksize(). 81 * gd->ram_size is deducted by the size of secure ram. 82 */ 83 dram_init_banksize(); 84 85 /* 86 * After dram_init_bank_size(), we know U-Boot only uses the first 87 * memory bank regardless how big the memory is. 88 */ 89 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 90 91 /* 92 * If PPA is loaded, U-Boot will resume running at EL2. 93 * Cache and MMU will be enabled. Need a place for TLB. 94 * U-Boot will be relocated to the end of available memory 95 * in first bank. At this point, we cannot know how much 96 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK 97 * to avoid overlapping. As soon as the RAM version U-Boot sets 98 * up new MMU, this space is no longer needed. 99 */ 100 gd->ram_top -= SPL_TLB_SETBACK; 101 gd->arch.tlb_size = PGTABLE_SIZE; 102 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); 103 gd->arch.tlb_allocated = gd->arch.tlb_addr; 104 #endif /* CONFIG_SPL_FSL_LS_PPA */ 105 } 106 107 #ifdef CONFIG_SPL_OS_BOOT 108 /* 109 * Return 110 * 0 if booting into OS is selected 111 * 1 if booting into U-Boot is selected 112 */ 113 int spl_start_uboot(void) 114 { 115 env_init(); 116 if (env_get_yesno("boot_os") != 0) 117 return 0; 118 119 return 1; 120 } 121 #endif /* CONFIG_SPL_OS_BOOT */ 122 #ifdef CONFIG_SPL_LOAD_FIT 123 int board_fit_config_name_match(const char *name) 124 { 125 /* Just empty function now - can't decide what to choose */ 126 debug("%s: %s\n", __func__, name); 127 128 return 0; 129 } 130 #endif 131 #endif /* CONFIG_SPL_BUILD */ 132