1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 #include <fsl_ddr_sdram.h> 16 #include <fsl_ddr.h> 17 #ifdef CONFIG_CHAIN_OF_TRUST 18 #include <fsl_validate.h> 19 #endif 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 bool soc_has_dp_ddr(void) 24 { 25 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 26 u32 svr = gur_in32(&gur->svr); 27 28 /* LS2085A has DP_DDR */ 29 if (SVR_SOC_VER(svr) == SVR_LS2085) 30 return true; 31 32 return false; 33 } 34 35 bool soc_has_aiop(void) 36 { 37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 38 u32 svr = gur_in32(&gur->svr); 39 40 /* LS2085A has AIOP */ 41 if (SVR_SOC_VER(svr) == SVR_LS2085) 42 return true; 43 44 return false; 45 } 46 47 #ifdef CONFIG_LS2080A 48 /* 49 * This erratum requires setting a value to eddrtqcr1 to 50 * optimal the DDR performance. 51 */ 52 static void erratum_a008336(void) 53 { 54 u32 *eddrtqcr1; 55 56 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 57 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 58 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 59 out_le32(eddrtqcr1, 0x63b30002); 60 #endif 61 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 62 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 63 out_le32(eddrtqcr1, 0x63b30002); 64 #endif 65 #endif 66 } 67 68 /* 69 * This erratum requires a register write before being Memory 70 * controller 3 being enabled. 71 */ 72 static void erratum_a008514(void) 73 { 74 u32 *eddrtqcr1; 75 76 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 77 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 78 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 79 out_le32(eddrtqcr1, 0x63b20002); 80 #endif 81 #endif 82 } 83 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 84 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 85 86 static unsigned long get_internval_val_mhz(void) 87 { 88 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 89 /* 90 * interval is the number of platform cycles(MHz) between 91 * wake up events generated by EPU. 92 */ 93 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 94 95 if (interval) 96 interval_mhz = simple_strtoul(interval, NULL, 10); 97 98 return interval_mhz; 99 } 100 101 void erratum_a009635(void) 102 { 103 u32 val; 104 unsigned long interval_mhz = get_internval_val_mhz(); 105 106 if (!interval_mhz) 107 return; 108 109 val = in_le32(DCSR_CGACRE5); 110 writel(val | 0x00000200, DCSR_CGACRE5); 111 112 val = in_le32(EPU_EPCMPR5); 113 writel(interval_mhz, EPU_EPCMPR5); 114 val = in_le32(EPU_EPCCR5); 115 writel(val | 0x82820000, EPU_EPCCR5); 116 val = in_le32(EPU_EPSMCR5); 117 writel(val | 0x002f0000, EPU_EPSMCR5); 118 val = in_le32(EPU_EPECR5); 119 writel(val | 0x20000000, EPU_EPECR5); 120 val = in_le32(EPU_EPGCR); 121 writel(val | 0x80000000, EPU_EPGCR); 122 } 123 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 124 125 static void erratum_a008751(void) 126 { 127 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 128 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 129 130 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); 131 #endif 132 } 133 134 static void erratum_rcw_src(void) 135 { 136 #if defined(CONFIG_SPL) 137 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 138 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 139 u32 val; 140 141 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 142 val &= ~DCFG_PORSR1_RCW_SRC; 143 val |= DCFG_PORSR1_RCW_SRC_NOR; 144 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 145 #endif 146 } 147 148 #define I2C_DEBUG_REG 0x6 149 #define I2C_GLITCH_EN 0x8 150 /* 151 * This erratum requires setting glitch_en bit to enable 152 * digital glitch filter to improve clock stability. 153 */ 154 static void erratum_a009203(void) 155 { 156 u8 __iomem *ptr; 157 #ifdef CONFIG_SYS_I2C 158 #ifdef I2C1_BASE_ADDR 159 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 160 161 writeb(I2C_GLITCH_EN, ptr); 162 #endif 163 #ifdef I2C2_BASE_ADDR 164 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 165 166 writeb(I2C_GLITCH_EN, ptr); 167 #endif 168 #ifdef I2C3_BASE_ADDR 169 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 170 171 writeb(I2C_GLITCH_EN, ptr); 172 #endif 173 #ifdef I2C4_BASE_ADDR 174 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 175 176 writeb(I2C_GLITCH_EN, ptr); 177 #endif 178 #endif 179 } 180 void bypass_smmu(void) 181 { 182 u32 val; 183 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 184 out_le32(SMMU_SCR0, val); 185 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 186 out_le32(SMMU_NSCR0, val); 187 } 188 void fsl_lsch3_early_init_f(void) 189 { 190 erratum_a008751(); 191 erratum_rcw_src(); 192 init_early_memctl_regs(); /* tighten IFC timing */ 193 erratum_a009203(); 194 erratum_a008514(); 195 erratum_a008336(); 196 #ifdef CONFIG_CHAIN_OF_TRUST 197 /* In case of Secure Boot, the IBR configures the SMMU 198 * to allow only Secure transactions. 199 * SMMU must be reset in bypass mode. 200 * Set the ClientPD bit and Clear the USFCFG Bit 201 */ 202 if (fsl_check_boot_mode_secure() == 1) 203 bypass_smmu(); 204 #endif 205 } 206 207 #ifdef CONFIG_SCSI_AHCI_PLAT 208 int sata_init(void) 209 { 210 struct ccsr_ahci __iomem *ccsr_ahci; 211 212 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 213 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 214 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 215 216 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 217 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 218 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 219 220 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 221 scsi_scan(0); 222 223 return 0; 224 } 225 #endif 226 227 #elif defined(CONFIG_LS1043A) 228 #ifdef CONFIG_SCSI_AHCI_PLAT 229 int sata_init(void) 230 { 231 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 232 233 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 234 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 235 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 236 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 237 238 ahci_init((void __iomem *)CONFIG_SYS_SATA); 239 scsi_scan(0); 240 241 return 0; 242 } 243 #endif 244 245 static void erratum_a009929(void) 246 { 247 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 248 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 249 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 250 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 251 252 rstrqmr1 |= 0x00000400; 253 gur_out32(&gur->rstrqmr1, rstrqmr1); 254 writel(0x01000000, dcsr_cop_ccp); 255 #endif 256 } 257 258 /* 259 * This erratum requires setting a value to eddrtqcr1 to optimal 260 * the DDR performance. The eddrtqcr1 register is in SCFG space 261 * of LS1043A and the offset is 0x157_020c. 262 */ 263 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 264 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 265 #error A009660 and A008514 can not be both enabled. 266 #endif 267 268 static void erratum_a009660(void) 269 { 270 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 271 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 272 out_be32(eddrtqcr1, 0x63b20042); 273 #endif 274 } 275 276 static void erratum_a008850_early(void) 277 { 278 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 279 /* part 1 of 2 */ 280 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 281 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 282 283 /* disables propagation of barrier transactions to DDRC from CCI400 */ 284 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 285 286 /* disable the re-ordering in DDRC */ 287 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 288 #endif 289 } 290 291 void erratum_a008850_post(void) 292 { 293 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 294 /* part 2 of 2 */ 295 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 296 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 297 u32 tmp; 298 299 /* enable propagation of barrier transactions to DDRC from CCI400 */ 300 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 301 302 /* enable the re-ordering in DDRC */ 303 tmp = ddr_in32(&ddr->eor); 304 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 305 ddr_out32(&ddr->eor, tmp); 306 #endif 307 } 308 309 void fsl_lsch2_early_init_f(void) 310 { 311 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 312 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 313 314 #ifdef CONFIG_FSL_IFC 315 init_early_memctl_regs(); /* tighten IFC timing */ 316 #endif 317 318 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 319 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 320 #endif 321 /* Make SEC reads and writes snoopable */ 322 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 323 SCFG_SNPCNFGCR_SECWRSNP); 324 325 /* 326 * Enable snoop requests and DVM message requests for 327 * Slave insterface S4 (A53 core cluster) 328 */ 329 out_le32(&cci->slave[4].snoop_ctrl, 330 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 331 332 /* Erratum */ 333 erratum_a008850_early(); /* part 1 of 2 */ 334 erratum_a009929(); 335 erratum_a009660(); 336 } 337 #endif 338 339 #ifdef CONFIG_BOARD_LATE_INIT 340 int board_late_init(void) 341 { 342 #ifdef CONFIG_SCSI_AHCI_PLAT 343 sata_init(); 344 #endif 345 #ifdef CONFIG_CHAIN_OF_TRUST 346 fsl_setenv_chain_of_trust(); 347 #endif 348 349 return 0; 350 } 351 #endif 352