1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 #ifdef CONFIG_CHAIN_OF_TRUST 16 #include <fsl_validate.h> 17 #endif 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 bool soc_has_dp_ddr(void) 22 { 23 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 24 u32 svr = gur_in32(&gur->svr); 25 26 /* LS2085A has DP_DDR */ 27 if (SVR_SOC_VER(svr) == SVR_LS2085) 28 return true; 29 30 return false; 31 } 32 33 bool soc_has_aiop(void) 34 { 35 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 36 u32 svr = gur_in32(&gur->svr); 37 38 /* LS2085A has AIOP */ 39 if (SVR_SOC_VER(svr) == SVR_LS2085) 40 return true; 41 42 return false; 43 } 44 45 #ifdef CONFIG_LS2080A 46 /* 47 * This erratum requires setting a value to eddrtqcr1 to 48 * optimal the DDR performance. 49 */ 50 static void erratum_a008336(void) 51 { 52 u32 *eddrtqcr1; 53 54 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 55 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 56 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 57 out_le32(eddrtqcr1, 0x63b30002); 58 #endif 59 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 60 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 61 out_le32(eddrtqcr1, 0x63b30002); 62 #endif 63 #endif 64 } 65 66 /* 67 * This erratum requires a register write before being Memory 68 * controller 3 being enabled. 69 */ 70 static void erratum_a008514(void) 71 { 72 u32 *eddrtqcr1; 73 74 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 75 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 76 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 77 out_le32(eddrtqcr1, 0x63b20002); 78 #endif 79 #endif 80 } 81 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 82 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 83 84 static unsigned long get_internval_val_mhz(void) 85 { 86 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 87 /* 88 * interval is the number of platform cycles(MHz) between 89 * wake up events generated by EPU. 90 */ 91 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 92 93 if (interval) 94 interval_mhz = simple_strtoul(interval, NULL, 10); 95 96 return interval_mhz; 97 } 98 99 void erratum_a009635(void) 100 { 101 u32 val; 102 unsigned long interval_mhz = get_internval_val_mhz(); 103 104 if (!interval_mhz) 105 return; 106 107 val = in_le32(DCSR_CGACRE5); 108 writel(val | 0x00000200, DCSR_CGACRE5); 109 110 val = in_le32(EPU_EPCMPR5); 111 writel(interval_mhz, EPU_EPCMPR5); 112 val = in_le32(EPU_EPCCR5); 113 writel(val | 0x82820000, EPU_EPCCR5); 114 val = in_le32(EPU_EPSMCR5); 115 writel(val | 0x002f0000, EPU_EPSMCR5); 116 val = in_le32(EPU_EPECR5); 117 writel(val | 0x20000000, EPU_EPECR5); 118 val = in_le32(EPU_EPGCR); 119 writel(val | 0x80000000, EPU_EPGCR); 120 } 121 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 122 123 static void erratum_a008751(void) 124 { 125 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 126 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 127 128 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); 129 #endif 130 } 131 132 static void erratum_rcw_src(void) 133 { 134 #if defined(CONFIG_SPL) 135 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 136 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 137 u32 val; 138 139 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 140 val &= ~DCFG_PORSR1_RCW_SRC; 141 val |= DCFG_PORSR1_RCW_SRC_NOR; 142 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 143 #endif 144 } 145 146 #define I2C_DEBUG_REG 0x6 147 #define I2C_GLITCH_EN 0x8 148 /* 149 * This erratum requires setting glitch_en bit to enable 150 * digital glitch filter to improve clock stability. 151 */ 152 static void erratum_a009203(void) 153 { 154 u8 __iomem *ptr; 155 #ifdef CONFIG_SYS_I2C 156 #ifdef I2C1_BASE_ADDR 157 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 158 159 writeb(I2C_GLITCH_EN, ptr); 160 #endif 161 #ifdef I2C2_BASE_ADDR 162 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 163 164 writeb(I2C_GLITCH_EN, ptr); 165 #endif 166 #ifdef I2C3_BASE_ADDR 167 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 168 169 writeb(I2C_GLITCH_EN, ptr); 170 #endif 171 #ifdef I2C4_BASE_ADDR 172 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 173 174 writeb(I2C_GLITCH_EN, ptr); 175 #endif 176 #endif 177 } 178 void bypass_smmu(void) 179 { 180 u32 val; 181 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 182 out_le32(SMMU_SCR0, val); 183 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 184 out_le32(SMMU_NSCR0, val); 185 } 186 void fsl_lsch3_early_init_f(void) 187 { 188 erratum_a008751(); 189 erratum_rcw_src(); 190 init_early_memctl_regs(); /* tighten IFC timing */ 191 erratum_a009203(); 192 erratum_a008514(); 193 erratum_a008336(); 194 #ifdef CONFIG_CHAIN_OF_TRUST 195 /* In case of Secure Boot, the IBR configures the SMMU 196 * to allow only Secure transactions. 197 * SMMU must be reset in bypass mode. 198 * Set the ClientPD bit and Clear the USFCFG Bit 199 */ 200 if (fsl_check_boot_mode_secure() == 1) 201 bypass_smmu(); 202 #endif 203 } 204 205 #ifdef CONFIG_SCSI_AHCI_PLAT 206 int sata_init(void) 207 { 208 struct ccsr_ahci __iomem *ccsr_ahci; 209 210 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 211 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 212 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 213 214 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 215 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 216 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 217 218 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 219 scsi_scan(0); 220 221 return 0; 222 } 223 #endif 224 225 #elif defined(CONFIG_LS1043A) 226 #ifdef CONFIG_SCSI_AHCI_PLAT 227 int sata_init(void) 228 { 229 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 230 231 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 232 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 233 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 234 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 235 236 ahci_init((void __iomem *)CONFIG_SYS_SATA); 237 scsi_scan(0); 238 239 return 0; 240 } 241 #endif 242 243 static void erratum_a009929(void) 244 { 245 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 246 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 247 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 248 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 249 250 rstrqmr1 |= 0x00000400; 251 gur_out32(&gur->rstrqmr1, rstrqmr1); 252 writel(0x01000000, dcsr_cop_ccp); 253 #endif 254 } 255 256 /* 257 * This erratum requires setting a value to eddrtqcr1 to optimal 258 * the DDR performance. The eddrtqcr1 register is in SCFG space 259 * of LS1043A and the offset is 0x157_020c. 260 */ 261 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 262 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 263 #error A009660 and A008514 can not be both enabled. 264 #endif 265 266 static void erratum_a009660(void) 267 { 268 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 269 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 270 out_be32(eddrtqcr1, 0x63b20042); 271 #endif 272 } 273 274 void fsl_lsch2_early_init_f(void) 275 { 276 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 277 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 278 279 #ifdef CONFIG_FSL_IFC 280 init_early_memctl_regs(); /* tighten IFC timing */ 281 #endif 282 283 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 284 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 285 #endif 286 /* Make SEC reads and writes snoopable */ 287 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 288 SCFG_SNPCNFGCR_SECWRSNP); 289 290 /* 291 * Enable snoop requests and DVM message requests for 292 * Slave insterface S4 (A53 core cluster) 293 */ 294 out_le32(&cci->slave[4].snoop_ctrl, 295 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 296 297 /* Erratum */ 298 erratum_a009929(); 299 erratum_a009660(); 300 } 301 #endif 302 303 #ifdef CONFIG_BOARD_LATE_INIT 304 int board_late_init(void) 305 { 306 #ifdef CONFIG_SCSI_AHCI_PLAT 307 sata_init(); 308 #endif 309 #ifdef CONFIG_CHAIN_OF_TRUST 310 fsl_setenv_chain_of_trust(); 311 #endif 312 313 return 0; 314 } 315 #endif 316