1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 19 /* 20 * This erratum requires setting a value to eddrtqcr1 to 21 * optimal the DDR performance. 22 */ 23 static void erratum_a008336(void) 24 { 25 u32 *eddrtqcr1; 26 27 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 28 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 29 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 30 out_le32(eddrtqcr1, 0x63b30002); 31 #endif 32 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 33 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 34 out_le32(eddrtqcr1, 0x63b30002); 35 #endif 36 #endif 37 } 38 39 /* 40 * This erratum requires a register write before being Memory 41 * controller 3 being enabled. 42 */ 43 static void erratum_a008514(void) 44 { 45 u32 *eddrtqcr1; 46 47 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 48 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 49 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 50 out_le32(eddrtqcr1, 0x63b20002); 51 #endif 52 #endif 53 } 54 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 55 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 56 57 static unsigned long get_internval_val_mhz(void) 58 { 59 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 60 /* 61 * interval is the number of platform cycles(MHz) between 62 * wake up events generated by EPU. 63 */ 64 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 65 66 if (interval) 67 interval_mhz = simple_strtoul(interval, NULL, 10); 68 69 return interval_mhz; 70 } 71 72 void erratum_a009635(void) 73 { 74 u32 val; 75 unsigned long interval_mhz = get_internval_val_mhz(); 76 77 if (!interval_mhz) 78 return; 79 80 val = in_le32(DCSR_CGACRE5); 81 writel(val | 0x00000200, DCSR_CGACRE5); 82 83 val = in_le32(EPU_EPCMPR5); 84 writel(interval_mhz, EPU_EPCMPR5); 85 val = in_le32(EPU_EPCCR5); 86 writel(val | 0x82820000, EPU_EPCCR5); 87 val = in_le32(EPU_EPSMCR5); 88 writel(val | 0x002f0000, EPU_EPSMCR5); 89 val = in_le32(EPU_EPECR5); 90 writel(val | 0x20000000, EPU_EPECR5); 91 val = in_le32(EPU_EPGCR); 92 writel(val | 0x80000000, EPU_EPGCR); 93 } 94 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 95 96 static void erratum_a008751(void) 97 { 98 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 99 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 100 101 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); 102 #endif 103 } 104 105 static void erratum_rcw_src(void) 106 { 107 #if defined(CONFIG_SPL) 108 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 109 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 110 u32 val; 111 112 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 113 val &= ~DCFG_PORSR1_RCW_SRC; 114 val |= DCFG_PORSR1_RCW_SRC_NOR; 115 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 116 #endif 117 } 118 119 #define I2C_DEBUG_REG 0x6 120 #define I2C_GLITCH_EN 0x8 121 /* 122 * This erratum requires setting glitch_en bit to enable 123 * digital glitch filter to improve clock stability. 124 */ 125 static void erratum_a009203(void) 126 { 127 u8 __iomem *ptr; 128 #ifdef CONFIG_SYS_I2C 129 #ifdef I2C1_BASE_ADDR 130 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 131 132 writeb(I2C_GLITCH_EN, ptr); 133 #endif 134 #ifdef I2C2_BASE_ADDR 135 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 136 137 writeb(I2C_GLITCH_EN, ptr); 138 #endif 139 #ifdef I2C3_BASE_ADDR 140 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 141 142 writeb(I2C_GLITCH_EN, ptr); 143 #endif 144 #ifdef I2C4_BASE_ADDR 145 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 146 147 writeb(I2C_GLITCH_EN, ptr); 148 #endif 149 #endif 150 } 151 152 void fsl_lsch3_early_init_f(void) 153 { 154 erratum_a008751(); 155 erratum_rcw_src(); 156 init_early_memctl_regs(); /* tighten IFC timing */ 157 erratum_a009203(); 158 erratum_a008514(); 159 erratum_a008336(); 160 } 161 162 #ifdef CONFIG_SCSI_AHCI_PLAT 163 int sata_init(void) 164 { 165 struct ccsr_ahci __iomem *ccsr_ahci; 166 167 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 168 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 169 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 170 171 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 172 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 173 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 174 175 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 176 scsi_scan(0); 177 178 return 0; 179 } 180 #endif 181 182 #elif defined(CONFIG_LS1043A) 183 #ifdef CONFIG_SCSI_AHCI_PLAT 184 int sata_init(void) 185 { 186 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 187 188 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 189 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 190 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 191 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 192 193 ahci_init((void __iomem *)CONFIG_SYS_SATA); 194 scsi_scan(0); 195 196 return 0; 197 } 198 #endif 199 200 void fsl_lsch2_early_init_f(void) 201 { 202 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 203 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 204 205 #ifdef CONFIG_FSL_IFC 206 init_early_memctl_regs(); /* tighten IFC timing */ 207 #endif 208 209 /* Make SEC reads and writes snoopable */ 210 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 211 SCFG_SNPCNFGCR_SECWRSNP); 212 213 /* 214 * Enable snoop requests and DVM message requests for 215 * Slave insterface S4 (A53 core cluster) 216 */ 217 out_le32(&cci->slave[4].snoop_ctrl, 218 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 219 } 220 #endif 221 222 #ifdef CONFIG_BOARD_LATE_INIT 223 int board_late_init(void) 224 { 225 #ifdef CONFIG_SCSI_AHCI_PLAT 226 sata_init(); 227 #endif 228 229 return 0; 230 } 231 #endif 232