1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 #ifdef CONFIG_SYS_FSL_DDR 16 #include <fsl_ddr_sdram.h> 17 #include <fsl_ddr.h> 18 #endif 19 #ifdef CONFIG_CHAIN_OF_TRUST 20 #include <fsl_validate.h> 21 #endif 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 bool soc_has_dp_ddr(void) 26 { 27 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 28 u32 svr = gur_in32(&gur->svr); 29 30 /* LS2085A has DP_DDR */ 31 if (SVR_SOC_VER(svr) == SVR_LS2085A) 32 return true; 33 34 return false; 35 } 36 37 bool soc_has_aiop(void) 38 { 39 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 40 u32 svr = gur_in32(&gur->svr); 41 42 /* LS2085A has AIOP */ 43 if (SVR_SOC_VER(svr) == SVR_LS2085A) 44 return true; 45 46 return false; 47 } 48 49 #ifdef CONFIG_LS2080A 50 /* 51 * This erratum requires setting a value to eddrtqcr1 to 52 * optimal the DDR performance. 53 */ 54 static void erratum_a008336(void) 55 { 56 u32 *eddrtqcr1; 57 58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 59 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 60 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 61 if (fsl_ddr_get_version(0) == 0x50200) 62 out_le32(eddrtqcr1, 0x63b30002); 63 #endif 64 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 65 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 66 if (fsl_ddr_get_version(0) == 0x50200) 67 out_le32(eddrtqcr1, 0x63b30002); 68 #endif 69 #endif 70 } 71 72 /* 73 * This erratum requires a register write before being Memory 74 * controller 3 being enabled. 75 */ 76 static void erratum_a008514(void) 77 { 78 u32 *eddrtqcr1; 79 80 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 81 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 82 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 83 out_le32(eddrtqcr1, 0x63b20002); 84 #endif 85 #endif 86 } 87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 88 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 89 90 static unsigned long get_internval_val_mhz(void) 91 { 92 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 93 /* 94 * interval is the number of platform cycles(MHz) between 95 * wake up events generated by EPU. 96 */ 97 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 98 99 if (interval) 100 interval_mhz = simple_strtoul(interval, NULL, 10); 101 102 return interval_mhz; 103 } 104 105 void erratum_a009635(void) 106 { 107 u32 val; 108 unsigned long interval_mhz = get_internval_val_mhz(); 109 110 if (!interval_mhz) 111 return; 112 113 val = in_le32(DCSR_CGACRE5); 114 writel(val | 0x00000200, DCSR_CGACRE5); 115 116 val = in_le32(EPU_EPCMPR5); 117 writel(interval_mhz, EPU_EPCMPR5); 118 val = in_le32(EPU_EPCCR5); 119 writel(val | 0x82820000, EPU_EPCCR5); 120 val = in_le32(EPU_EPSMCR5); 121 writel(val | 0x002f0000, EPU_EPSMCR5); 122 val = in_le32(EPU_EPECR5); 123 writel(val | 0x20000000, EPU_EPECR5); 124 val = in_le32(EPU_EPGCR); 125 writel(val | 0x80000000, EPU_EPGCR); 126 } 127 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 128 129 static void erratum_rcw_src(void) 130 { 131 #if defined(CONFIG_SPL) 132 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 133 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 134 u32 val; 135 136 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 137 val &= ~DCFG_PORSR1_RCW_SRC; 138 val |= DCFG_PORSR1_RCW_SRC_NOR; 139 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 140 #endif 141 } 142 143 #define I2C_DEBUG_REG 0x6 144 #define I2C_GLITCH_EN 0x8 145 /* 146 * This erratum requires setting glitch_en bit to enable 147 * digital glitch filter to improve clock stability. 148 */ 149 static void erratum_a009203(void) 150 { 151 u8 __iomem *ptr; 152 #ifdef CONFIG_SYS_I2C 153 #ifdef I2C1_BASE_ADDR 154 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 155 156 writeb(I2C_GLITCH_EN, ptr); 157 #endif 158 #ifdef I2C2_BASE_ADDR 159 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 160 161 writeb(I2C_GLITCH_EN, ptr); 162 #endif 163 #ifdef I2C3_BASE_ADDR 164 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 165 166 writeb(I2C_GLITCH_EN, ptr); 167 #endif 168 #ifdef I2C4_BASE_ADDR 169 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 170 171 writeb(I2C_GLITCH_EN, ptr); 172 #endif 173 #endif 174 } 175 void bypass_smmu(void) 176 { 177 u32 val; 178 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 179 out_le32(SMMU_SCR0, val); 180 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 181 out_le32(SMMU_NSCR0, val); 182 } 183 void fsl_lsch3_early_init_f(void) 184 { 185 erratum_rcw_src(); 186 init_early_memctl_regs(); /* tighten IFC timing */ 187 erratum_a009203(); 188 erratum_a008514(); 189 erratum_a008336(); 190 #ifdef CONFIG_CHAIN_OF_TRUST 191 /* In case of Secure Boot, the IBR configures the SMMU 192 * to allow only Secure transactions. 193 * SMMU must be reset in bypass mode. 194 * Set the ClientPD bit and Clear the USFCFG Bit 195 */ 196 if (fsl_check_boot_mode_secure() == 1) 197 bypass_smmu(); 198 #endif 199 } 200 201 #ifdef CONFIG_SCSI_AHCI_PLAT 202 int sata_init(void) 203 { 204 struct ccsr_ahci __iomem *ccsr_ahci; 205 206 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 207 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 208 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 209 210 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 211 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 212 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 213 214 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 215 scsi_scan(0); 216 217 return 0; 218 } 219 #endif 220 221 #elif defined(CONFIG_FSL_LSCH2) 222 #ifdef CONFIG_SCSI_AHCI_PLAT 223 int sata_init(void) 224 { 225 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 226 227 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 228 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 229 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 230 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 231 232 ahci_init((void __iomem *)CONFIG_SYS_SATA); 233 scsi_scan(0); 234 235 return 0; 236 } 237 #endif 238 239 static void erratum_a009929(void) 240 { 241 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 242 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 243 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 244 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 245 246 rstrqmr1 |= 0x00000400; 247 gur_out32(&gur->rstrqmr1, rstrqmr1); 248 writel(0x01000000, dcsr_cop_ccp); 249 #endif 250 } 251 252 /* 253 * This erratum requires setting a value to eddrtqcr1 to optimal 254 * the DDR performance. The eddrtqcr1 register is in SCFG space 255 * of LS1043A and the offset is 0x157_020c. 256 */ 257 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 258 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 259 #error A009660 and A008514 can not be both enabled. 260 #endif 261 262 static void erratum_a009660(void) 263 { 264 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 265 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 266 out_be32(eddrtqcr1, 0x63b20042); 267 #endif 268 } 269 270 static void erratum_a008850_early(void) 271 { 272 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 273 /* part 1 of 2 */ 274 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 275 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 276 277 /* disables propagation of barrier transactions to DDRC from CCI400 */ 278 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 279 280 /* disable the re-ordering in DDRC */ 281 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 282 #endif 283 } 284 285 void erratum_a008850_post(void) 286 { 287 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 288 /* part 2 of 2 */ 289 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 290 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 291 u32 tmp; 292 293 /* enable propagation of barrier transactions to DDRC from CCI400 */ 294 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 295 296 /* enable the re-ordering in DDRC */ 297 tmp = ddr_in32(&ddr->eor); 298 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 299 ddr_out32(&ddr->eor, tmp); 300 #endif 301 } 302 303 void fsl_lsch2_early_init_f(void) 304 { 305 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 306 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 307 308 #ifdef CONFIG_FSL_IFC 309 init_early_memctl_regs(); /* tighten IFC timing */ 310 #endif 311 312 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 313 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 314 #endif 315 /* Make SEC reads and writes snoopable */ 316 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 317 SCFG_SNPCNFGCR_SECWRSNP); 318 319 /* 320 * Enable snoop requests and DVM message requests for 321 * Slave insterface S4 (A53 core cluster) 322 */ 323 out_le32(&cci->slave[4].snoop_ctrl, 324 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 325 326 /* Erratum */ 327 erratum_a008850_early(); /* part 1 of 2 */ 328 erratum_a009929(); 329 erratum_a009660(); 330 } 331 #endif 332 333 #ifdef CONFIG_BOARD_LATE_INIT 334 int board_late_init(void) 335 { 336 #ifdef CONFIG_SCSI_AHCI_PLAT 337 sata_init(); 338 #endif 339 #ifdef CONFIG_CHAIN_OF_TRUST 340 fsl_setenv_chain_of_trust(); 341 #endif 342 343 return 0; 344 } 345 #endif 346