1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <asm/io.h> 14 #include <asm/global_data.h> 15 #include <asm/arch-fsl-layerscape/config.h> 16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 17 #include <fsl_csu.h> 18 #endif 19 #ifdef CONFIG_SYS_FSL_DDR 20 #include <fsl_ddr_sdram.h> 21 #include <fsl_ddr.h> 22 #endif 23 #ifdef CONFIG_CHAIN_OF_TRUST 24 #include <fsl_validate.h> 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 bool soc_has_dp_ddr(void) 30 { 31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 32 u32 svr = gur_in32(&gur->svr); 33 34 /* LS2085A, LS2088A, LS2048A has DP_DDR */ 35 if ((SVR_SOC_VER(svr) == SVR_LS2085A) || 36 (SVR_SOC_VER(svr) == SVR_LS2088A) || 37 (SVR_SOC_VER(svr) == SVR_LS2048A)) 38 return true; 39 40 return false; 41 } 42 43 bool soc_has_aiop(void) 44 { 45 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 46 u32 svr = gur_in32(&gur->svr); 47 48 /* LS2085A has AIOP */ 49 if (SVR_SOC_VER(svr) == SVR_LS2085A) 50 return true; 51 52 return false; 53 } 54 55 #if defined(CONFIG_FSL_LSCH3) 56 /* 57 * This erratum requires setting a value to eddrtqcr1 to 58 * optimal the DDR performance. 59 */ 60 static void erratum_a008336(void) 61 { 62 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 63 u32 *eddrtqcr1; 64 65 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 66 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 67 if (fsl_ddr_get_version(0) == 0x50200) 68 out_le32(eddrtqcr1, 0x63b30002); 69 #endif 70 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 71 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 72 if (fsl_ddr_get_version(0) == 0x50200) 73 out_le32(eddrtqcr1, 0x63b30002); 74 #endif 75 #endif 76 } 77 78 /* 79 * This erratum requires a register write before being Memory 80 * controller 3 being enabled. 81 */ 82 static void erratum_a008514(void) 83 { 84 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 85 u32 *eddrtqcr1; 86 87 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 88 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 89 out_le32(eddrtqcr1, 0x63b20002); 90 #endif 91 #endif 92 } 93 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 94 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 95 96 static unsigned long get_internval_val_mhz(void) 97 { 98 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 99 /* 100 * interval is the number of platform cycles(MHz) between 101 * wake up events generated by EPU. 102 */ 103 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 104 105 if (interval) 106 interval_mhz = simple_strtoul(interval, NULL, 10); 107 108 return interval_mhz; 109 } 110 111 void erratum_a009635(void) 112 { 113 u32 val; 114 unsigned long interval_mhz = get_internval_val_mhz(); 115 116 if (!interval_mhz) 117 return; 118 119 val = in_le32(DCSR_CGACRE5); 120 writel(val | 0x00000200, DCSR_CGACRE5); 121 122 val = in_le32(EPU_EPCMPR5); 123 writel(interval_mhz, EPU_EPCMPR5); 124 val = in_le32(EPU_EPCCR5); 125 writel(val | 0x82820000, EPU_EPCCR5); 126 val = in_le32(EPU_EPSMCR5); 127 writel(val | 0x002f0000, EPU_EPSMCR5); 128 val = in_le32(EPU_EPECR5); 129 writel(val | 0x20000000, EPU_EPECR5); 130 val = in_le32(EPU_EPGCR); 131 writel(val | 0x80000000, EPU_EPGCR); 132 } 133 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 134 135 static void erratum_rcw_src(void) 136 { 137 #if defined(CONFIG_SPL) 138 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 139 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 140 u32 val; 141 142 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 143 val &= ~DCFG_PORSR1_RCW_SRC; 144 val |= DCFG_PORSR1_RCW_SRC_NOR; 145 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 146 #endif 147 } 148 149 #define I2C_DEBUG_REG 0x6 150 #define I2C_GLITCH_EN 0x8 151 /* 152 * This erratum requires setting glitch_en bit to enable 153 * digital glitch filter to improve clock stability. 154 */ 155 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 156 static void erratum_a009203(void) 157 { 158 u8 __iomem *ptr; 159 #ifdef CONFIG_SYS_I2C 160 #ifdef I2C1_BASE_ADDR 161 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 162 163 writeb(I2C_GLITCH_EN, ptr); 164 #endif 165 #ifdef I2C2_BASE_ADDR 166 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 167 168 writeb(I2C_GLITCH_EN, ptr); 169 #endif 170 #ifdef I2C3_BASE_ADDR 171 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 172 173 writeb(I2C_GLITCH_EN, ptr); 174 #endif 175 #ifdef I2C4_BASE_ADDR 176 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 177 178 writeb(I2C_GLITCH_EN, ptr); 179 #endif 180 #endif 181 } 182 #endif 183 184 void bypass_smmu(void) 185 { 186 u32 val; 187 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 188 out_le32(SMMU_SCR0, val); 189 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 190 out_le32(SMMU_NSCR0, val); 191 } 192 void fsl_lsch3_early_init_f(void) 193 { 194 erratum_rcw_src(); 195 init_early_memctl_regs(); /* tighten IFC timing */ 196 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 197 erratum_a009203(); 198 #endif 199 erratum_a008514(); 200 erratum_a008336(); 201 #ifdef CONFIG_CHAIN_OF_TRUST 202 /* In case of Secure Boot, the IBR configures the SMMU 203 * to allow only Secure transactions. 204 * SMMU must be reset in bypass mode. 205 * Set the ClientPD bit and Clear the USFCFG Bit 206 */ 207 if (fsl_check_boot_mode_secure() == 1) 208 bypass_smmu(); 209 #endif 210 } 211 212 #ifdef CONFIG_SCSI_AHCI_PLAT 213 int sata_init(void) 214 { 215 struct ccsr_ahci __iomem *ccsr_ahci; 216 217 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 218 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 219 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 220 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 221 222 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 223 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 224 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 225 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 226 227 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 228 scsi_scan(0); 229 230 return 0; 231 } 232 #endif 233 234 #elif defined(CONFIG_FSL_LSCH2) 235 #ifdef CONFIG_SCSI_AHCI_PLAT 236 int sata_init(void) 237 { 238 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 239 240 /* Disable SATA ECC */ 241 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); 242 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 243 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 244 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 245 246 ahci_init((void __iomem *)CONFIG_SYS_SATA); 247 scsi_scan(0); 248 249 return 0; 250 } 251 #endif 252 253 static void erratum_a009929(void) 254 { 255 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 256 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 257 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 258 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 259 260 rstrqmr1 |= 0x00000400; 261 gur_out32(&gur->rstrqmr1, rstrqmr1); 262 writel(0x01000000, dcsr_cop_ccp); 263 #endif 264 } 265 266 /* 267 * This erratum requires setting a value to eddrtqcr1 to optimal 268 * the DDR performance. The eddrtqcr1 register is in SCFG space 269 * of LS1043A and the offset is 0x157_020c. 270 */ 271 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 272 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 273 #error A009660 and A008514 can not be both enabled. 274 #endif 275 276 static void erratum_a009660(void) 277 { 278 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 279 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 280 out_be32(eddrtqcr1, 0x63b20042); 281 #endif 282 } 283 284 static void erratum_a008850_early(void) 285 { 286 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 287 /* part 1 of 2 */ 288 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 289 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 290 291 /* disables propagation of barrier transactions to DDRC from CCI400 */ 292 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 293 294 /* disable the re-ordering in DDRC */ 295 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 296 #endif 297 } 298 299 void erratum_a008850_post(void) 300 { 301 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 302 /* part 2 of 2 */ 303 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 304 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 305 u32 tmp; 306 307 /* enable propagation of barrier transactions to DDRC from CCI400 */ 308 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 309 310 /* enable the re-ordering in DDRC */ 311 tmp = ddr_in32(&ddr->eor); 312 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 313 ddr_out32(&ddr->eor, tmp); 314 #endif 315 } 316 317 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 318 void erratum_a010315(void) 319 { 320 int i; 321 322 for (i = PCIE1; i <= PCIE4; i++) 323 if (!is_serdes_configured(i)) { 324 debug("PCIe%d: disabled all R/W permission!\n", i); 325 set_pcie_ns_access(i, 0); 326 } 327 } 328 #endif 329 330 static void erratum_a010539(void) 331 { 332 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 333 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 334 u32 porsr1; 335 336 porsr1 = in_be32(&gur->porsr1); 337 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 338 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 339 porsr1); 340 #endif 341 } 342 343 /* Get VDD in the unit mV from voltage ID */ 344 int get_core_volt_from_fuse(void) 345 { 346 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 347 int vdd; 348 u32 fusesr; 349 u8 vid; 350 351 fusesr = in_be32(&gur->dcfg_fusesr); 352 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 353 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & 354 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; 355 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { 356 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & 357 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; 358 } 359 debug("%s: VID = 0x%x\n", __func__, vid); 360 switch (vid) { 361 case 0x00: /* VID isn't supported */ 362 vdd = -EINVAL; 363 debug("%s: The VID feature is not supported\n", __func__); 364 break; 365 case 0x08: /* 0.9V silicon */ 366 vdd = 900; 367 break; 368 case 0x10: /* 1.0V silicon */ 369 vdd = 1000; 370 break; 371 default: /* Other core voltage */ 372 vdd = -EINVAL; 373 printf("%s: The VID(%x) isn't supported\n", __func__, vid); 374 break; 375 } 376 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 377 378 return vdd; 379 } 380 381 __weak int board_switch_core_volt(u32 vdd) 382 { 383 return 0; 384 } 385 386 static int setup_core_volt(u32 vdd) 387 { 388 return board_setup_core_volt(vdd); 389 } 390 391 #ifdef CONFIG_SYS_FSL_DDR 392 static void ddr_enable_0v9_volt(bool en) 393 { 394 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 395 u32 tmp; 396 397 tmp = ddr_in32(&ddr->ddr_cdr1); 398 399 if (en) 400 tmp |= DDR_CDR1_V0PT9_EN; 401 else 402 tmp &= ~DDR_CDR1_V0PT9_EN; 403 404 ddr_out32(&ddr->ddr_cdr1, tmp); 405 } 406 #endif 407 408 int setup_chip_volt(void) 409 { 410 int vdd; 411 412 vdd = get_core_volt_from_fuse(); 413 /* Nothing to do for silicons doesn't support VID */ 414 if (vdd < 0) 415 return vdd; 416 417 if (setup_core_volt(vdd)) 418 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); 419 #ifdef CONFIG_SYS_HAS_SERDES 420 if (setup_serdes_volt(vdd)) 421 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); 422 #endif 423 424 #ifdef CONFIG_SYS_FSL_DDR 425 if (vdd == 900) 426 ddr_enable_0v9_volt(true); 427 #endif 428 429 return 0; 430 } 431 432 void fsl_lsch2_early_init_f(void) 433 { 434 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 435 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 436 437 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 438 enable_layerscape_ns_access(); 439 #endif 440 441 #ifdef CONFIG_FSL_IFC 442 init_early_memctl_regs(); /* tighten IFC timing */ 443 #endif 444 445 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 446 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 447 #endif 448 /* Make SEC reads and writes snoopable */ 449 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 450 SCFG_SNPCNFGCR_SECWRSNP | 451 SCFG_SNPCNFGCR_SATARDSNP | 452 SCFG_SNPCNFGCR_SATAWRSNP); 453 454 /* 455 * Enable snoop requests and DVM message requests for 456 * Slave insterface S4 (A53 core cluster) 457 */ 458 out_le32(&cci->slave[4].snoop_ctrl, 459 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 460 461 /* Erratum */ 462 erratum_a008850_early(); /* part 1 of 2 */ 463 erratum_a009929(); 464 erratum_a009660(); 465 erratum_a010539(); 466 } 467 #endif 468 469 #ifdef CONFIG_QSPI_AHB_INIT 470 /* Enable 4bytes address support and fast read */ 471 int qspi_ahb_init(void) 472 { 473 u32 *qspi_lut, lut_key, *qspi_key; 474 475 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; 476 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; 477 478 lut_key = in_be32(qspi_key); 479 480 if (lut_key == 0x5af05af0) { 481 /* That means the register is BE */ 482 out_be32(qspi_key, 0x5af05af0); 483 /* Unlock the lut table */ 484 out_be32(qspi_key + 1, 0x00000002); 485 out_be32(qspi_lut, 0x0820040c); 486 out_be32(qspi_lut + 1, 0x1c080c08); 487 out_be32(qspi_lut + 2, 0x00002400); 488 /* Lock the lut table */ 489 out_be32(qspi_key, 0x5af05af0); 490 out_be32(qspi_key + 1, 0x00000001); 491 } else { 492 /* That means the register is LE */ 493 out_le32(qspi_key, 0x5af05af0); 494 /* Unlock the lut table */ 495 out_le32(qspi_key + 1, 0x00000002); 496 out_le32(qspi_lut, 0x0820040c); 497 out_le32(qspi_lut + 1, 0x1c080c08); 498 out_le32(qspi_lut + 2, 0x00002400); 499 /* Lock the lut table */ 500 out_le32(qspi_key, 0x5af05af0); 501 out_le32(qspi_key + 1, 0x00000001); 502 } 503 504 return 0; 505 } 506 #endif 507 508 #ifdef CONFIG_BOARD_LATE_INIT 509 int board_late_init(void) 510 { 511 #ifdef CONFIG_SCSI_AHCI_PLAT 512 sata_init(); 513 #endif 514 #ifdef CONFIG_CHAIN_OF_TRUST 515 fsl_setenv_chain_of_trust(); 516 #endif 517 #ifdef CONFIG_QSPI_AHB_INIT 518 qspi_ahb_init(); 519 #endif 520 521 return 0; 522 } 523 #endif 524