1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <asm/io.h> 14 #include <asm/global_data.h> 15 #include <asm/arch-fsl-layerscape/config.h> 16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 17 #include <fsl_csu.h> 18 #endif 19 #ifdef CONFIG_SYS_FSL_DDR 20 #include <fsl_ddr_sdram.h> 21 #include <fsl_ddr.h> 22 #endif 23 #ifdef CONFIG_CHAIN_OF_TRUST 24 #include <fsl_validate.h> 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 bool soc_has_dp_ddr(void) 30 { 31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 32 u32 svr = gur_in32(&gur->svr); 33 34 /* LS2085A has DP_DDR */ 35 if (SVR_SOC_VER(svr) == SVR_LS2085A) 36 return true; 37 38 return false; 39 } 40 41 bool soc_has_aiop(void) 42 { 43 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 44 u32 svr = gur_in32(&gur->svr); 45 46 /* LS2085A has AIOP */ 47 if (SVR_SOC_VER(svr) == SVR_LS2085A) 48 return true; 49 50 return false; 51 } 52 53 #ifdef CONFIG_LS2080A 54 /* 55 * This erratum requires setting a value to eddrtqcr1 to 56 * optimal the DDR performance. 57 */ 58 static void erratum_a008336(void) 59 { 60 u32 *eddrtqcr1; 61 62 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 63 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 64 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 65 if (fsl_ddr_get_version(0) == 0x50200) 66 out_le32(eddrtqcr1, 0x63b30002); 67 #endif 68 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 69 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 70 if (fsl_ddr_get_version(0) == 0x50200) 71 out_le32(eddrtqcr1, 0x63b30002); 72 #endif 73 #endif 74 } 75 76 /* 77 * This erratum requires a register write before being Memory 78 * controller 3 being enabled. 79 */ 80 static void erratum_a008514(void) 81 { 82 u32 *eddrtqcr1; 83 84 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 85 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 86 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 87 out_le32(eddrtqcr1, 0x63b20002); 88 #endif 89 #endif 90 } 91 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 92 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 93 94 static unsigned long get_internval_val_mhz(void) 95 { 96 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 97 /* 98 * interval is the number of platform cycles(MHz) between 99 * wake up events generated by EPU. 100 */ 101 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 102 103 if (interval) 104 interval_mhz = simple_strtoul(interval, NULL, 10); 105 106 return interval_mhz; 107 } 108 109 void erratum_a009635(void) 110 { 111 u32 val; 112 unsigned long interval_mhz = get_internval_val_mhz(); 113 114 if (!interval_mhz) 115 return; 116 117 val = in_le32(DCSR_CGACRE5); 118 writel(val | 0x00000200, DCSR_CGACRE5); 119 120 val = in_le32(EPU_EPCMPR5); 121 writel(interval_mhz, EPU_EPCMPR5); 122 val = in_le32(EPU_EPCCR5); 123 writel(val | 0x82820000, EPU_EPCCR5); 124 val = in_le32(EPU_EPSMCR5); 125 writel(val | 0x002f0000, EPU_EPSMCR5); 126 val = in_le32(EPU_EPECR5); 127 writel(val | 0x20000000, EPU_EPECR5); 128 val = in_le32(EPU_EPGCR); 129 writel(val | 0x80000000, EPU_EPGCR); 130 } 131 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 132 133 static void erratum_rcw_src(void) 134 { 135 #if defined(CONFIG_SPL) 136 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 137 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 138 u32 val; 139 140 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 141 val &= ~DCFG_PORSR1_RCW_SRC; 142 val |= DCFG_PORSR1_RCW_SRC_NOR; 143 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 144 #endif 145 } 146 147 #define I2C_DEBUG_REG 0x6 148 #define I2C_GLITCH_EN 0x8 149 /* 150 * This erratum requires setting glitch_en bit to enable 151 * digital glitch filter to improve clock stability. 152 */ 153 static void erratum_a009203(void) 154 { 155 u8 __iomem *ptr; 156 #ifdef CONFIG_SYS_I2C 157 #ifdef I2C1_BASE_ADDR 158 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 159 160 writeb(I2C_GLITCH_EN, ptr); 161 #endif 162 #ifdef I2C2_BASE_ADDR 163 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 164 165 writeb(I2C_GLITCH_EN, ptr); 166 #endif 167 #ifdef I2C3_BASE_ADDR 168 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 169 170 writeb(I2C_GLITCH_EN, ptr); 171 #endif 172 #ifdef I2C4_BASE_ADDR 173 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 174 175 writeb(I2C_GLITCH_EN, ptr); 176 #endif 177 #endif 178 } 179 void bypass_smmu(void) 180 { 181 u32 val; 182 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 183 out_le32(SMMU_SCR0, val); 184 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 185 out_le32(SMMU_NSCR0, val); 186 } 187 void fsl_lsch3_early_init_f(void) 188 { 189 erratum_rcw_src(); 190 init_early_memctl_regs(); /* tighten IFC timing */ 191 erratum_a009203(); 192 erratum_a008514(); 193 erratum_a008336(); 194 #ifdef CONFIG_CHAIN_OF_TRUST 195 /* In case of Secure Boot, the IBR configures the SMMU 196 * to allow only Secure transactions. 197 * SMMU must be reset in bypass mode. 198 * Set the ClientPD bit and Clear the USFCFG Bit 199 */ 200 if (fsl_check_boot_mode_secure() == 1) 201 bypass_smmu(); 202 #endif 203 } 204 205 #ifdef CONFIG_SCSI_AHCI_PLAT 206 int sata_init(void) 207 { 208 struct ccsr_ahci __iomem *ccsr_ahci; 209 210 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 211 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 212 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 213 214 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 215 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 216 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 217 218 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 219 scsi_scan(0); 220 221 return 0; 222 } 223 #endif 224 225 #elif defined(CONFIG_FSL_LSCH2) 226 #ifdef CONFIG_SCSI_AHCI_PLAT 227 int sata_init(void) 228 { 229 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 230 231 #ifdef CONFIG_ARCH_LS1046A 232 /* Disable SATA ECC */ 233 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); 234 #endif 235 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 236 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 237 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 238 239 ahci_init((void __iomem *)CONFIG_SYS_SATA); 240 scsi_scan(0); 241 242 return 0; 243 } 244 #endif 245 246 static void erratum_a009929(void) 247 { 248 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 249 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 250 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 251 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 252 253 rstrqmr1 |= 0x00000400; 254 gur_out32(&gur->rstrqmr1, rstrqmr1); 255 writel(0x01000000, dcsr_cop_ccp); 256 #endif 257 } 258 259 /* 260 * This erratum requires setting a value to eddrtqcr1 to optimal 261 * the DDR performance. The eddrtqcr1 register is in SCFG space 262 * of LS1043A and the offset is 0x157_020c. 263 */ 264 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 265 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 266 #error A009660 and A008514 can not be both enabled. 267 #endif 268 269 static void erratum_a009660(void) 270 { 271 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 272 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 273 out_be32(eddrtqcr1, 0x63b20042); 274 #endif 275 } 276 277 static void erratum_a008850_early(void) 278 { 279 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 280 /* part 1 of 2 */ 281 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 282 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 283 284 /* disables propagation of barrier transactions to DDRC from CCI400 */ 285 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 286 287 /* disable the re-ordering in DDRC */ 288 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 289 #endif 290 } 291 292 void erratum_a008850_post(void) 293 { 294 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 295 /* part 2 of 2 */ 296 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 297 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 298 u32 tmp; 299 300 /* enable propagation of barrier transactions to DDRC from CCI400 */ 301 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 302 303 /* enable the re-ordering in DDRC */ 304 tmp = ddr_in32(&ddr->eor); 305 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 306 ddr_out32(&ddr->eor, tmp); 307 #endif 308 } 309 310 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 311 void erratum_a010315(void) 312 { 313 int i; 314 315 for (i = PCIE1; i <= PCIE4; i++) 316 if (!is_serdes_configured(i)) { 317 debug("PCIe%d: disabled all R/W permission!\n", i); 318 set_pcie_ns_access(i, 0); 319 } 320 } 321 #endif 322 323 static void erratum_a010539(void) 324 { 325 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 326 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 327 u32 porsr1; 328 329 porsr1 = in_be32(&gur->porsr1); 330 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 331 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 332 porsr1); 333 #endif 334 } 335 336 void fsl_lsch2_early_init_f(void) 337 { 338 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 339 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 340 341 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 342 enable_layerscape_ns_access(); 343 #endif 344 345 #ifdef CONFIG_FSL_IFC 346 init_early_memctl_regs(); /* tighten IFC timing */ 347 #endif 348 349 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 350 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 351 #endif 352 /* Make SEC reads and writes snoopable */ 353 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 354 SCFG_SNPCNFGCR_SECWRSNP | 355 SCFG_SNPCNFGCR_SATARDSNP | 356 SCFG_SNPCNFGCR_SATAWRSNP); 357 358 /* 359 * Enable snoop requests and DVM message requests for 360 * Slave insterface S4 (A53 core cluster) 361 */ 362 out_le32(&cci->slave[4].snoop_ctrl, 363 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 364 365 /* Erratum */ 366 erratum_a008850_early(); /* part 1 of 2 */ 367 erratum_a009929(); 368 erratum_a009660(); 369 erratum_a010539(); 370 } 371 #endif 372 373 #ifdef CONFIG_BOARD_LATE_INIT 374 int board_late_init(void) 375 { 376 #ifdef CONFIG_SCSI_AHCI_PLAT 377 sata_init(); 378 #endif 379 #ifdef CONFIG_CHAIN_OF_TRUST 380 fsl_setenv_chain_of_trust(); 381 #endif 382 383 return 0; 384 } 385 #endif 386