1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_immap.h> 9 #include <fsl_ifc.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/soc.h> 14 #include <asm/io.h> 15 #include <asm/global_data.h> 16 #include <asm/arch-fsl-layerscape/config.h> 17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 18 #include <fsl_csu.h> 19 #endif 20 #ifdef CONFIG_SYS_FSL_DDR 21 #include <fsl_ddr_sdram.h> 22 #include <fsl_ddr.h> 23 #endif 24 #ifdef CONFIG_CHAIN_OF_TRUST 25 #include <fsl_validate.h> 26 #endif 27 #include <fsl_immap.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 bool soc_has_dp_ddr(void) 32 { 33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 34 u32 svr = gur_in32(&gur->svr); 35 36 /* LS2085A, LS2088A, LS2048A has DP_DDR */ 37 if ((SVR_SOC_VER(svr) == SVR_LS2085A) || 38 (SVR_SOC_VER(svr) == SVR_LS2088A) || 39 (SVR_SOC_VER(svr) == SVR_LS2048A)) 40 return true; 41 42 return false; 43 } 44 45 bool soc_has_aiop(void) 46 { 47 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 48 u32 svr = gur_in32(&gur->svr); 49 50 /* LS2085A has AIOP */ 51 if (SVR_SOC_VER(svr) == SVR_LS2085A) 52 return true; 53 54 return false; 55 } 56 57 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) 58 { 59 scfg_clrsetbits32(scfg + offset / 4, 60 0xF << 6, 61 SCFG_USB_TXVREFTUNE << 6); 62 } 63 64 static void erratum_a009008(void) 65 { 66 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 67 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 68 69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 70 defined(CONFIG_ARCH_LS1012A) 71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); 72 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 73 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); 74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); 75 #endif 76 #elif defined(CONFIG_ARCH_LS2080A) 77 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); 78 #endif 79 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ 80 } 81 82 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) 83 { 84 scfg_clrbits32(scfg + offset / 4, 85 SCFG_USB_SQRXTUNE_MASK << 23); 86 } 87 88 static void erratum_a009798(void) 89 { 90 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 91 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 92 93 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 94 defined(CONFIG_ARCH_LS1012A) 95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); 96 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 97 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); 98 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); 99 #endif 100 #elif defined(CONFIG_ARCH_LS2080A) 101 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); 102 #endif 103 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ 104 } 105 106 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 107 defined(CONFIG_ARCH_LS1012A) 108 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) 109 { 110 scfg_clrsetbits32(scfg + offset / 4, 111 0x7F << 9, 112 SCFG_USB_PCSTXSWINGFULL << 9); 113 } 114 #endif 115 116 static void erratum_a008997(void) 117 { 118 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 119 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 120 defined(CONFIG_ARCH_LS1012A) 121 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 122 123 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); 124 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 125 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); 126 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); 127 #endif 128 #endif 129 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ 130 } 131 132 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 133 defined(CONFIG_ARCH_LS1012A) 134 135 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 136 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 137 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 138 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 139 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 140 141 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 142 143 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 144 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 145 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 146 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 147 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 148 149 #endif 150 151 static void erratum_a009007(void) 152 { 153 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 154 defined(CONFIG_ARCH_LS1012A) 155 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; 156 157 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 158 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 159 usb_phy = (void __iomem *)SCFG_USB_PHY2; 160 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 161 162 usb_phy = (void __iomem *)SCFG_USB_PHY3; 163 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 164 #endif 165 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 166 void __iomem *dcsr = (void __iomem *)DCSR_BASE; 167 168 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); 169 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); 170 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ 171 } 172 173 #if defined(CONFIG_FSL_LSCH3) 174 /* 175 * This erratum requires setting a value to eddrtqcr1 to 176 * optimal the DDR performance. 177 */ 178 static void erratum_a008336(void) 179 { 180 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 181 u32 *eddrtqcr1; 182 183 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 184 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 185 if (fsl_ddr_get_version(0) == 0x50200) 186 out_le32(eddrtqcr1, 0x63b30002); 187 #endif 188 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 189 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 190 if (fsl_ddr_get_version(0) == 0x50200) 191 out_le32(eddrtqcr1, 0x63b30002); 192 #endif 193 #endif 194 } 195 196 /* 197 * This erratum requires a register write before being Memory 198 * controller 3 being enabled. 199 */ 200 static void erratum_a008514(void) 201 { 202 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 203 u32 *eddrtqcr1; 204 205 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 206 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 207 out_le32(eddrtqcr1, 0x63b20002); 208 #endif 209 #endif 210 } 211 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 212 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 213 214 static unsigned long get_internval_val_mhz(void) 215 { 216 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); 217 /* 218 * interval is the number of platform cycles(MHz) between 219 * wake up events generated by EPU. 220 */ 221 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 222 223 if (interval) 224 interval_mhz = simple_strtoul(interval, NULL, 10); 225 226 return interval_mhz; 227 } 228 229 void erratum_a009635(void) 230 { 231 u32 val; 232 unsigned long interval_mhz = get_internval_val_mhz(); 233 234 if (!interval_mhz) 235 return; 236 237 val = in_le32(DCSR_CGACRE5); 238 writel(val | 0x00000200, DCSR_CGACRE5); 239 240 val = in_le32(EPU_EPCMPR5); 241 writel(interval_mhz, EPU_EPCMPR5); 242 val = in_le32(EPU_EPCCR5); 243 writel(val | 0x82820000, EPU_EPCCR5); 244 val = in_le32(EPU_EPSMCR5); 245 writel(val | 0x002f0000, EPU_EPSMCR5); 246 val = in_le32(EPU_EPECR5); 247 writel(val | 0x20000000, EPU_EPECR5); 248 val = in_le32(EPU_EPGCR); 249 writel(val | 0x80000000, EPU_EPGCR); 250 } 251 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 252 253 static void erratum_rcw_src(void) 254 { 255 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) 256 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 257 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 258 u32 val; 259 260 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 261 val &= ~DCFG_PORSR1_RCW_SRC; 262 val |= DCFG_PORSR1_RCW_SRC_NOR; 263 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 264 #endif 265 } 266 267 #define I2C_DEBUG_REG 0x6 268 #define I2C_GLITCH_EN 0x8 269 /* 270 * This erratum requires setting glitch_en bit to enable 271 * digital glitch filter to improve clock stability. 272 */ 273 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 274 static void erratum_a009203(void) 275 { 276 #ifdef CONFIG_SYS_I2C 277 u8 __iomem *ptr; 278 #ifdef I2C1_BASE_ADDR 279 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 280 281 writeb(I2C_GLITCH_EN, ptr); 282 #endif 283 #ifdef I2C2_BASE_ADDR 284 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 285 286 writeb(I2C_GLITCH_EN, ptr); 287 #endif 288 #ifdef I2C3_BASE_ADDR 289 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 290 291 writeb(I2C_GLITCH_EN, ptr); 292 #endif 293 #ifdef I2C4_BASE_ADDR 294 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 295 296 writeb(I2C_GLITCH_EN, ptr); 297 #endif 298 #endif 299 } 300 #endif 301 302 void bypass_smmu(void) 303 { 304 u32 val; 305 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 306 out_le32(SMMU_SCR0, val); 307 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 308 out_le32(SMMU_NSCR0, val); 309 } 310 void fsl_lsch3_early_init_f(void) 311 { 312 erratum_rcw_src(); 313 #ifdef CONFIG_FSL_IFC 314 init_early_memctl_regs(); /* tighten IFC timing */ 315 #endif 316 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 317 erratum_a009203(); 318 #endif 319 erratum_a008514(); 320 erratum_a008336(); 321 erratum_a009008(); 322 erratum_a009798(); 323 erratum_a008997(); 324 erratum_a009007(); 325 #ifdef CONFIG_CHAIN_OF_TRUST 326 /* In case of Secure Boot, the IBR configures the SMMU 327 * to allow only Secure transactions. 328 * SMMU must be reset in bypass mode. 329 * Set the ClientPD bit and Clear the USFCFG Bit 330 */ 331 if (fsl_check_boot_mode_secure() == 1) 332 bypass_smmu(); 333 #endif 334 } 335 336 #ifdef CONFIG_SCSI_AHCI_PLAT 337 int sata_init(void) 338 { 339 struct ccsr_ahci __iomem *ccsr_ahci; 340 341 #ifdef CONFIG_SYS_SATA2 342 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 343 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 344 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 345 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 346 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 347 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 348 #endif 349 350 #ifdef CONFIG_SYS_SATA1 351 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 352 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 353 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 354 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 355 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 356 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 357 358 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 359 scsi_scan(false); 360 #endif 361 362 return 0; 363 } 364 #endif 365 366 /* Get VDD in the unit mV from voltage ID */ 367 int get_core_volt_from_fuse(void) 368 { 369 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 370 int vdd; 371 u32 fusesr; 372 u8 vid; 373 374 /* get the voltage ID from fuse status register */ 375 fusesr = in_le32(&gur->dcfg_fusesr); 376 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 377 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & 378 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; 379 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { 380 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & 381 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; 382 } 383 debug("%s: VID = 0x%x\n", __func__, vid); 384 switch (vid) { 385 case 0x00: /* VID isn't supported */ 386 vdd = -EINVAL; 387 debug("%s: The VID feature is not supported\n", __func__); 388 break; 389 case 0x08: /* 0.9V silicon */ 390 vdd = 900; 391 break; 392 case 0x10: /* 1.0V silicon */ 393 vdd = 1000; 394 break; 395 default: /* Other core voltage */ 396 vdd = -EINVAL; 397 debug("%s: The VID(%x) isn't supported\n", __func__, vid); 398 break; 399 } 400 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 401 402 return vdd; 403 } 404 405 #elif defined(CONFIG_FSL_LSCH2) 406 #ifdef CONFIG_SCSI_AHCI_PLAT 407 int sata_init(void) 408 { 409 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 410 411 /* Disable SATA ECC */ 412 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); 413 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 414 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 415 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 416 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 417 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 418 419 ahci_init((void __iomem *)CONFIG_SYS_SATA); 420 scsi_scan(false); 421 422 return 0; 423 } 424 #endif 425 426 static void erratum_a009929(void) 427 { 428 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 429 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 430 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 431 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 432 433 rstrqmr1 |= 0x00000400; 434 gur_out32(&gur->rstrqmr1, rstrqmr1); 435 writel(0x01000000, dcsr_cop_ccp); 436 #endif 437 } 438 439 /* 440 * This erratum requires setting a value to eddrtqcr1 to optimal 441 * the DDR performance. The eddrtqcr1 register is in SCFG space 442 * of LS1043A and the offset is 0x157_020c. 443 */ 444 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 445 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 446 #error A009660 and A008514 can not be both enabled. 447 #endif 448 449 static void erratum_a009660(void) 450 { 451 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 452 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 453 out_be32(eddrtqcr1, 0x63b20042); 454 #endif 455 } 456 457 static void erratum_a008850_early(void) 458 { 459 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 460 /* part 1 of 2 */ 461 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 462 CONFIG_SYS_CCI400_OFFSET); 463 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 464 465 /* Skip if running at lower exception level */ 466 if (current_el() < 3) 467 return; 468 469 /* disables propagation of barrier transactions to DDRC from CCI400 */ 470 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 471 472 /* disable the re-ordering in DDRC */ 473 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 474 #endif 475 } 476 477 void erratum_a008850_post(void) 478 { 479 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 480 /* part 2 of 2 */ 481 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 482 CONFIG_SYS_CCI400_OFFSET); 483 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 484 u32 tmp; 485 486 /* Skip if running at lower exception level */ 487 if (current_el() < 3) 488 return; 489 490 /* enable propagation of barrier transactions to DDRC from CCI400 */ 491 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 492 493 /* enable the re-ordering in DDRC */ 494 tmp = ddr_in32(&ddr->eor); 495 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 496 ddr_out32(&ddr->eor, tmp); 497 #endif 498 } 499 500 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 501 void erratum_a010315(void) 502 { 503 int i; 504 505 for (i = PCIE1; i <= PCIE4; i++) 506 if (!is_serdes_configured(i)) { 507 debug("PCIe%d: disabled all R/W permission!\n", i); 508 set_pcie_ns_access(i, 0); 509 } 510 } 511 #endif 512 513 static void erratum_a010539(void) 514 { 515 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 516 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 517 u32 porsr1; 518 519 porsr1 = in_be32(&gur->porsr1); 520 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 521 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 522 porsr1); 523 #endif 524 } 525 526 /* Get VDD in the unit mV from voltage ID */ 527 int get_core_volt_from_fuse(void) 528 { 529 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 530 int vdd; 531 u32 fusesr; 532 u8 vid; 533 534 fusesr = in_be32(&gur->dcfg_fusesr); 535 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 536 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & 537 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; 538 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { 539 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & 540 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; 541 } 542 debug("%s: VID = 0x%x\n", __func__, vid); 543 switch (vid) { 544 case 0x00: /* VID isn't supported */ 545 vdd = -EINVAL; 546 debug("%s: The VID feature is not supported\n", __func__); 547 break; 548 case 0x08: /* 0.9V silicon */ 549 vdd = 900; 550 break; 551 case 0x10: /* 1.0V silicon */ 552 vdd = 1000; 553 break; 554 default: /* Other core voltage */ 555 vdd = -EINVAL; 556 printf("%s: The VID(%x) isn't supported\n", __func__, vid); 557 break; 558 } 559 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 560 561 return vdd; 562 } 563 564 __weak int board_switch_core_volt(u32 vdd) 565 { 566 return 0; 567 } 568 569 static int setup_core_volt(u32 vdd) 570 { 571 return board_setup_core_volt(vdd); 572 } 573 574 #ifdef CONFIG_SYS_FSL_DDR 575 static void ddr_enable_0v9_volt(bool en) 576 { 577 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 578 u32 tmp; 579 580 tmp = ddr_in32(&ddr->ddr_cdr1); 581 582 if (en) 583 tmp |= DDR_CDR1_V0PT9_EN; 584 else 585 tmp &= ~DDR_CDR1_V0PT9_EN; 586 587 ddr_out32(&ddr->ddr_cdr1, tmp); 588 } 589 #endif 590 591 int setup_chip_volt(void) 592 { 593 int vdd; 594 595 vdd = get_core_volt_from_fuse(); 596 /* Nothing to do for silicons doesn't support VID */ 597 if (vdd < 0) 598 return vdd; 599 600 if (setup_core_volt(vdd)) 601 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); 602 #ifdef CONFIG_SYS_HAS_SERDES 603 if (setup_serdes_volt(vdd)) 604 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); 605 #endif 606 607 #ifdef CONFIG_SYS_FSL_DDR 608 if (vdd == 900) 609 ddr_enable_0v9_volt(true); 610 #endif 611 612 return 0; 613 } 614 615 void fsl_lsch2_early_init_f(void) 616 { 617 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 618 CONFIG_SYS_CCI400_OFFSET); 619 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 620 621 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 622 enable_layerscape_ns_access(); 623 #endif 624 625 #ifdef CONFIG_FSL_IFC 626 init_early_memctl_regs(); /* tighten IFC timing */ 627 #endif 628 629 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 630 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 631 #endif 632 /* Make SEC reads and writes snoopable */ 633 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 634 SCFG_SNPCNFGCR_SECWRSNP | 635 SCFG_SNPCNFGCR_SATARDSNP | 636 SCFG_SNPCNFGCR_SATAWRSNP); 637 638 /* 639 * Enable snoop requests and DVM message requests for 640 * Slave insterface S4 (A53 core cluster) 641 */ 642 if (current_el() == 3) { 643 out_le32(&cci->slave[4].snoop_ctrl, 644 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 645 } 646 647 /* Erratum */ 648 erratum_a008850_early(); /* part 1 of 2 */ 649 erratum_a009929(); 650 erratum_a009660(); 651 erratum_a010539(); 652 erratum_a009008(); 653 erratum_a009798(); 654 erratum_a008997(); 655 erratum_a009007(); 656 } 657 #endif 658 659 #ifdef CONFIG_QSPI_AHB_INIT 660 /* Enable 4bytes address support and fast read */ 661 int qspi_ahb_init(void) 662 { 663 u32 *qspi_lut, lut_key, *qspi_key; 664 665 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; 666 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; 667 668 lut_key = in_be32(qspi_key); 669 670 if (lut_key == 0x5af05af0) { 671 /* That means the register is BE */ 672 out_be32(qspi_key, 0x5af05af0); 673 /* Unlock the lut table */ 674 out_be32(qspi_key + 1, 0x00000002); 675 out_be32(qspi_lut, 0x0820040c); 676 out_be32(qspi_lut + 1, 0x1c080c08); 677 out_be32(qspi_lut + 2, 0x00002400); 678 /* Lock the lut table */ 679 out_be32(qspi_key, 0x5af05af0); 680 out_be32(qspi_key + 1, 0x00000001); 681 } else { 682 /* That means the register is LE */ 683 out_le32(qspi_key, 0x5af05af0); 684 /* Unlock the lut table */ 685 out_le32(qspi_key + 1, 0x00000002); 686 out_le32(qspi_lut, 0x0820040c); 687 out_le32(qspi_lut + 1, 0x1c080c08); 688 out_le32(qspi_lut + 2, 0x00002400); 689 /* Lock the lut table */ 690 out_le32(qspi_key, 0x5af05af0); 691 out_le32(qspi_key + 1, 0x00000001); 692 } 693 694 return 0; 695 } 696 #endif 697 698 #ifdef CONFIG_BOARD_LATE_INIT 699 int board_late_init(void) 700 { 701 #ifdef CONFIG_SCSI_AHCI_PLAT 702 sata_init(); 703 #endif 704 #ifdef CONFIG_CHAIN_OF_TRUST 705 fsl_setenv_chain_of_trust(); 706 #endif 707 #ifdef CONFIG_QSPI_AHB_INIT 708 qspi_ahb_init(); 709 #endif 710 711 return 0; 712 } 713 #endif 714