1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014-2015 Freescale Semiconductor 4 */ 5 6 #include <common.h> 7 #include <fsl_immap.h> 8 #include <fsl_ifc.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <asm/arch/soc.h> 11 #include <asm/io.h> 12 #include <asm/global_data.h> 13 #include <asm/arch-fsl-layerscape/config.h> 14 #include <asm/arch-fsl-layerscape/ns_access.h> 15 #include <asm/arch-fsl-layerscape/fsl_icid.h> 16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 17 #include <fsl_csu.h> 18 #endif 19 #ifdef CONFIG_SYS_FSL_DDR 20 #include <fsl_ddr_sdram.h> 21 #include <fsl_ddr.h> 22 #endif 23 #ifdef CONFIG_CHAIN_OF_TRUST 24 #include <fsl_validate.h> 25 #endif 26 #include <fsl_immap.h> 27 28 bool soc_has_dp_ddr(void) 29 { 30 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 31 u32 svr = gur_in32(&gur->svr); 32 33 /* LS2085A, LS2088A, LS2048A has DP_DDR */ 34 if ((SVR_SOC_VER(svr) == SVR_LS2085A) || 35 (SVR_SOC_VER(svr) == SVR_LS2088A) || 36 (SVR_SOC_VER(svr) == SVR_LS2048A)) 37 return true; 38 39 return false; 40 } 41 42 bool soc_has_aiop(void) 43 { 44 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 45 u32 svr = gur_in32(&gur->svr); 46 47 /* LS2085A has AIOP */ 48 if (SVR_SOC_VER(svr) == SVR_LS2085A) 49 return true; 50 51 return false; 52 } 53 54 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) 55 { 56 scfg_clrsetbits32(scfg + offset / 4, 57 0xF << 6, 58 SCFG_USB_TXVREFTUNE << 6); 59 } 60 61 static void erratum_a009008(void) 62 { 63 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 64 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 65 66 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 67 defined(CONFIG_ARCH_LS1012A) 68 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); 69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 70 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); 71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); 72 #endif 73 #elif defined(CONFIG_ARCH_LS2080A) 74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); 75 #endif 76 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ 77 } 78 79 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) 80 { 81 scfg_clrbits32(scfg + offset / 4, 82 SCFG_USB_SQRXTUNE_MASK << 23); 83 } 84 85 static void erratum_a009798(void) 86 { 87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 88 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 89 90 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 91 defined(CONFIG_ARCH_LS1012A) 92 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); 93 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 94 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); 95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); 96 #endif 97 #elif defined(CONFIG_ARCH_LS2080A) 98 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); 99 #endif 100 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ 101 } 102 103 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 104 defined(CONFIG_ARCH_LS1012A) 105 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) 106 { 107 scfg_clrsetbits32(scfg + offset / 4, 108 0x7F << 9, 109 SCFG_USB_PCSTXSWINGFULL << 9); 110 } 111 #endif 112 113 static void erratum_a008997(void) 114 { 115 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 116 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 117 defined(CONFIG_ARCH_LS1012A) 118 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 119 120 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); 121 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 122 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); 123 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); 124 #endif 125 #endif 126 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ 127 } 128 129 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 130 defined(CONFIG_ARCH_LS1012A) 131 132 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 133 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 134 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 135 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 136 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 137 138 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 139 140 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 141 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 142 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 143 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 144 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 145 146 #endif 147 148 static void erratum_a009007(void) 149 { 150 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 151 defined(CONFIG_ARCH_LS1012A) 152 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; 153 154 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 155 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 156 usb_phy = (void __iomem *)SCFG_USB_PHY2; 157 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 158 159 usb_phy = (void __iomem *)SCFG_USB_PHY3; 160 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 161 #endif 162 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 163 void __iomem *dcsr = (void __iomem *)DCSR_BASE; 164 165 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); 166 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); 167 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ 168 } 169 170 #if defined(CONFIG_FSL_LSCH3) 171 /* 172 * This erratum requires setting a value to eddrtqcr1 to 173 * optimal the DDR performance. 174 */ 175 static void erratum_a008336(void) 176 { 177 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 178 u32 *eddrtqcr1; 179 180 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 181 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 182 if (fsl_ddr_get_version(0) == 0x50200) 183 out_le32(eddrtqcr1, 0x63b30002); 184 #endif 185 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 186 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 187 if (fsl_ddr_get_version(0) == 0x50200) 188 out_le32(eddrtqcr1, 0x63b30002); 189 #endif 190 #endif 191 } 192 193 /* 194 * This erratum requires a register write before being Memory 195 * controller 3 being enabled. 196 */ 197 static void erratum_a008514(void) 198 { 199 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 200 u32 *eddrtqcr1; 201 202 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 203 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 204 out_le32(eddrtqcr1, 0x63b20002); 205 #endif 206 #endif 207 } 208 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 209 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 210 211 static unsigned long get_internval_val_mhz(void) 212 { 213 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); 214 /* 215 * interval is the number of platform cycles(MHz) between 216 * wake up events generated by EPU. 217 */ 218 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 219 220 if (interval) 221 interval_mhz = simple_strtoul(interval, NULL, 10); 222 223 return interval_mhz; 224 } 225 226 void erratum_a009635(void) 227 { 228 u32 val; 229 unsigned long interval_mhz = get_internval_val_mhz(); 230 231 if (!interval_mhz) 232 return; 233 234 val = in_le32(DCSR_CGACRE5); 235 writel(val | 0x00000200, DCSR_CGACRE5); 236 237 val = in_le32(EPU_EPCMPR5); 238 writel(interval_mhz, EPU_EPCMPR5); 239 val = in_le32(EPU_EPCCR5); 240 writel(val | 0x82820000, EPU_EPCCR5); 241 val = in_le32(EPU_EPSMCR5); 242 writel(val | 0x002f0000, EPU_EPSMCR5); 243 val = in_le32(EPU_EPECR5); 244 writel(val | 0x20000000, EPU_EPECR5); 245 val = in_le32(EPU_EPGCR); 246 writel(val | 0x80000000, EPU_EPGCR); 247 } 248 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 249 250 static void erratum_rcw_src(void) 251 { 252 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) 253 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 254 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 255 u32 val; 256 257 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 258 val &= ~DCFG_PORSR1_RCW_SRC; 259 val |= DCFG_PORSR1_RCW_SRC_NOR; 260 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 261 #endif 262 } 263 264 #define I2C_DEBUG_REG 0x6 265 #define I2C_GLITCH_EN 0x8 266 /* 267 * This erratum requires setting glitch_en bit to enable 268 * digital glitch filter to improve clock stability. 269 */ 270 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 271 static void erratum_a009203(void) 272 { 273 #ifdef CONFIG_SYS_I2C 274 u8 __iomem *ptr; 275 #ifdef I2C1_BASE_ADDR 276 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 277 278 writeb(I2C_GLITCH_EN, ptr); 279 #endif 280 #ifdef I2C2_BASE_ADDR 281 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 282 283 writeb(I2C_GLITCH_EN, ptr); 284 #endif 285 #ifdef I2C3_BASE_ADDR 286 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 287 288 writeb(I2C_GLITCH_EN, ptr); 289 #endif 290 #ifdef I2C4_BASE_ADDR 291 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 292 293 writeb(I2C_GLITCH_EN, ptr); 294 #endif 295 #endif 296 } 297 #endif 298 299 void bypass_smmu(void) 300 { 301 u32 val; 302 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 303 out_le32(SMMU_SCR0, val); 304 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 305 out_le32(SMMU_NSCR0, val); 306 } 307 void fsl_lsch3_early_init_f(void) 308 { 309 erratum_rcw_src(); 310 #ifdef CONFIG_FSL_IFC 311 init_early_memctl_regs(); /* tighten IFC timing */ 312 #endif 313 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 314 erratum_a009203(); 315 #endif 316 erratum_a008514(); 317 erratum_a008336(); 318 erratum_a009008(); 319 erratum_a009798(); 320 erratum_a008997(); 321 erratum_a009007(); 322 #ifdef CONFIG_CHAIN_OF_TRUST 323 /* In case of Secure Boot, the IBR configures the SMMU 324 * to allow only Secure transactions. 325 * SMMU must be reset in bypass mode. 326 * Set the ClientPD bit and Clear the USFCFG Bit 327 */ 328 if (fsl_check_boot_mode_secure() == 1) 329 bypass_smmu(); 330 #endif 331 } 332 333 /* Get VDD in the unit mV from voltage ID */ 334 int get_core_volt_from_fuse(void) 335 { 336 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 337 int vdd; 338 u32 fusesr; 339 u8 vid; 340 341 /* get the voltage ID from fuse status register */ 342 fusesr = in_le32(&gur->dcfg_fusesr); 343 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 344 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & 345 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; 346 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { 347 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & 348 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; 349 } 350 debug("%s: VID = 0x%x\n", __func__, vid); 351 switch (vid) { 352 case 0x00: /* VID isn't supported */ 353 vdd = -EINVAL; 354 debug("%s: The VID feature is not supported\n", __func__); 355 break; 356 case 0x08: /* 0.9V silicon */ 357 vdd = 900; 358 break; 359 case 0x10: /* 1.0V silicon */ 360 vdd = 1000; 361 break; 362 default: /* Other core voltage */ 363 vdd = -EINVAL; 364 debug("%s: The VID(%x) isn't supported\n", __func__, vid); 365 break; 366 } 367 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 368 369 return vdd; 370 } 371 372 #elif defined(CONFIG_FSL_LSCH2) 373 374 static void erratum_a009929(void) 375 { 376 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 377 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 378 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 379 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 380 381 rstrqmr1 |= 0x00000400; 382 gur_out32(&gur->rstrqmr1, rstrqmr1); 383 writel(0x01000000, dcsr_cop_ccp); 384 #endif 385 } 386 387 /* 388 * This erratum requires setting a value to eddrtqcr1 to optimal 389 * the DDR performance. The eddrtqcr1 register is in SCFG space 390 * of LS1043A and the offset is 0x157_020c. 391 */ 392 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 393 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 394 #error A009660 and A008514 can not be both enabled. 395 #endif 396 397 static void erratum_a009660(void) 398 { 399 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 400 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 401 out_be32(eddrtqcr1, 0x63b20042); 402 #endif 403 } 404 405 static void erratum_a008850_early(void) 406 { 407 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 408 /* part 1 of 2 */ 409 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 410 CONFIG_SYS_CCI400_OFFSET); 411 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 412 413 /* Skip if running at lower exception level */ 414 if (current_el() < 3) 415 return; 416 417 /* disables propagation of barrier transactions to DDRC from CCI400 */ 418 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 419 420 /* disable the re-ordering in DDRC */ 421 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 422 #endif 423 } 424 425 void erratum_a008850_post(void) 426 { 427 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 428 /* part 2 of 2 */ 429 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 430 CONFIG_SYS_CCI400_OFFSET); 431 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 432 u32 tmp; 433 434 /* Skip if running at lower exception level */ 435 if (current_el() < 3) 436 return; 437 438 /* enable propagation of barrier transactions to DDRC from CCI400 */ 439 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 440 441 /* enable the re-ordering in DDRC */ 442 tmp = ddr_in32(&ddr->eor); 443 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 444 ddr_out32(&ddr->eor, tmp); 445 #endif 446 } 447 448 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 449 void erratum_a010315(void) 450 { 451 int i; 452 453 for (i = PCIE1; i <= PCIE4; i++) 454 if (!is_serdes_configured(i)) { 455 debug("PCIe%d: disabled all R/W permission!\n", i); 456 set_pcie_ns_access(i, 0); 457 } 458 } 459 #endif 460 461 static void erratum_a010539(void) 462 { 463 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 464 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 465 u32 porsr1; 466 467 porsr1 = in_be32(&gur->porsr1); 468 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 469 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 470 porsr1); 471 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); 472 #endif 473 } 474 475 /* Get VDD in the unit mV from voltage ID */ 476 int get_core_volt_from_fuse(void) 477 { 478 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 479 int vdd; 480 u32 fusesr; 481 u8 vid; 482 483 fusesr = in_be32(&gur->dcfg_fusesr); 484 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 485 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & 486 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; 487 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { 488 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & 489 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; 490 } 491 debug("%s: VID = 0x%x\n", __func__, vid); 492 switch (vid) { 493 case 0x00: /* VID isn't supported */ 494 vdd = -EINVAL; 495 debug("%s: The VID feature is not supported\n", __func__); 496 break; 497 case 0x08: /* 0.9V silicon */ 498 vdd = 900; 499 break; 500 case 0x10: /* 1.0V silicon */ 501 vdd = 1000; 502 break; 503 default: /* Other core voltage */ 504 vdd = -EINVAL; 505 printf("%s: The VID(%x) isn't supported\n", __func__, vid); 506 break; 507 } 508 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 509 510 return vdd; 511 } 512 513 __weak int board_switch_core_volt(u32 vdd) 514 { 515 return 0; 516 } 517 518 static int setup_core_volt(u32 vdd) 519 { 520 return board_setup_core_volt(vdd); 521 } 522 523 #ifdef CONFIG_SYS_FSL_DDR 524 static void ddr_enable_0v9_volt(bool en) 525 { 526 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 527 u32 tmp; 528 529 tmp = ddr_in32(&ddr->ddr_cdr1); 530 531 if (en) 532 tmp |= DDR_CDR1_V0PT9_EN; 533 else 534 tmp &= ~DDR_CDR1_V0PT9_EN; 535 536 ddr_out32(&ddr->ddr_cdr1, tmp); 537 } 538 #endif 539 540 int setup_chip_volt(void) 541 { 542 int vdd; 543 544 vdd = get_core_volt_from_fuse(); 545 /* Nothing to do for silicons doesn't support VID */ 546 if (vdd < 0) 547 return vdd; 548 549 if (setup_core_volt(vdd)) 550 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); 551 #ifdef CONFIG_SYS_HAS_SERDES 552 if (setup_serdes_volt(vdd)) 553 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); 554 #endif 555 556 #ifdef CONFIG_SYS_FSL_DDR 557 if (vdd == 900) 558 ddr_enable_0v9_volt(true); 559 #endif 560 561 return 0; 562 } 563 564 #ifdef CONFIG_FSL_PFE 565 void init_pfe_scfg_dcfg_regs(void) 566 { 567 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 568 u32 ecccr2; 569 570 out_be32(&scfg->pfeasbcr, 571 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); 572 out_be32(&scfg->pfebsbcr, 573 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); 574 575 /* CCI-400 QoS settings for PFE */ 576 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS 577 | SCFG_WR_QOS1_PFE2_QOS)); 578 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS 579 | SCFG_RD_QOS1_PFE2_QOS)); 580 581 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); 582 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, 583 ecccr2 | (unsigned int)DISABLE_PFE_ECC); 584 } 585 #endif 586 587 void fsl_lsch2_early_init_f(void) 588 { 589 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 590 CONFIG_SYS_CCI400_OFFSET); 591 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 592 593 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 594 enable_layerscape_ns_access(); 595 #endif 596 597 #ifdef CONFIG_FSL_IFC 598 init_early_memctl_regs(); /* tighten IFC timing */ 599 #endif 600 601 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 602 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 603 #endif 604 /* Make SEC reads and writes snoopable */ 605 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 606 SCFG_SNPCNFGCR_SECWRSNP | 607 SCFG_SNPCNFGCR_SATARDSNP | 608 SCFG_SNPCNFGCR_SATAWRSNP); 609 610 /* 611 * Enable snoop requests and DVM message requests for 612 * Slave insterface S4 (A53 core cluster) 613 */ 614 if (current_el() == 3) { 615 out_le32(&cci->slave[4].snoop_ctrl, 616 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 617 } 618 619 /* 620 * Program Central Security Unit (CSU) to grant access 621 * permission for USB 2.0 controller 622 */ 623 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL) 624 if (current_el() == 3) 625 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); 626 #endif 627 /* Erratum */ 628 erratum_a008850_early(); /* part 1 of 2 */ 629 erratum_a009929(); 630 erratum_a009660(); 631 erratum_a010539(); 632 erratum_a009008(); 633 erratum_a009798(); 634 erratum_a008997(); 635 erratum_a009007(); 636 637 #ifdef CONFIG_ARCH_LS1046A 638 set_icids(); 639 #endif 640 } 641 #endif 642 643 #ifdef CONFIG_QSPI_AHB_INIT 644 /* Enable 4bytes address support and fast read */ 645 int qspi_ahb_init(void) 646 { 647 u32 *qspi_lut, lut_key, *qspi_key; 648 649 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; 650 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; 651 652 lut_key = in_be32(qspi_key); 653 654 if (lut_key == 0x5af05af0) { 655 /* That means the register is BE */ 656 out_be32(qspi_key, 0x5af05af0); 657 /* Unlock the lut table */ 658 out_be32(qspi_key + 1, 0x00000002); 659 out_be32(qspi_lut, 0x0820040c); 660 out_be32(qspi_lut + 1, 0x1c080c08); 661 out_be32(qspi_lut + 2, 0x00002400); 662 /* Lock the lut table */ 663 out_be32(qspi_key, 0x5af05af0); 664 out_be32(qspi_key + 1, 0x00000001); 665 } else { 666 /* That means the register is LE */ 667 out_le32(qspi_key, 0x5af05af0); 668 /* Unlock the lut table */ 669 out_le32(qspi_key + 1, 0x00000002); 670 out_le32(qspi_lut, 0x0820040c); 671 out_le32(qspi_lut + 1, 0x1c080c08); 672 out_le32(qspi_lut + 2, 0x00002400); 673 /* Lock the lut table */ 674 out_le32(qspi_key, 0x5af05af0); 675 out_le32(qspi_key + 1, 0x00000001); 676 } 677 678 return 0; 679 } 680 #endif 681 682 #ifdef CONFIG_BOARD_LATE_INIT 683 int board_late_init(void) 684 { 685 #ifdef CONFIG_CHAIN_OF_TRUST 686 fsl_setenv_chain_of_trust(); 687 #endif 688 #ifdef CONFIG_QSPI_AHB_INIT 689 qspi_ahb_init(); 690 #endif 691 692 return 0; 693 } 694 #endif 695