1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 #ifdef CONFIG_SYS_FSL_DDR 16 #include <fsl_ddr_sdram.h> 17 #include <fsl_ddr.h> 18 #endif 19 #ifdef CONFIG_CHAIN_OF_TRUST 20 #include <fsl_validate.h> 21 #endif 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 bool soc_has_dp_ddr(void) 26 { 27 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 28 u32 svr = gur_in32(&gur->svr); 29 30 /* LS2085A has DP_DDR */ 31 if (SVR_SOC_VER(svr) == SVR_LS2085) 32 return true; 33 34 return false; 35 } 36 37 bool soc_has_aiop(void) 38 { 39 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 40 u32 svr = gur_in32(&gur->svr); 41 42 /* LS2085A has AIOP */ 43 if (SVR_SOC_VER(svr) == SVR_LS2085) 44 return true; 45 46 return false; 47 } 48 49 #ifdef CONFIG_LS2080A 50 /* 51 * This erratum requires setting a value to eddrtqcr1 to 52 * optimal the DDR performance. 53 */ 54 static void erratum_a008336(void) 55 { 56 u32 *eddrtqcr1; 57 58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 59 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 60 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 61 out_le32(eddrtqcr1, 0x63b30002); 62 #endif 63 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 64 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 65 out_le32(eddrtqcr1, 0x63b30002); 66 #endif 67 #endif 68 } 69 70 /* 71 * This erratum requires a register write before being Memory 72 * controller 3 being enabled. 73 */ 74 static void erratum_a008514(void) 75 { 76 u32 *eddrtqcr1; 77 78 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 79 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 80 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 81 out_le32(eddrtqcr1, 0x63b20002); 82 #endif 83 #endif 84 } 85 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 86 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 87 88 static unsigned long get_internval_val_mhz(void) 89 { 90 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 91 /* 92 * interval is the number of platform cycles(MHz) between 93 * wake up events generated by EPU. 94 */ 95 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 96 97 if (interval) 98 interval_mhz = simple_strtoul(interval, NULL, 10); 99 100 return interval_mhz; 101 } 102 103 void erratum_a009635(void) 104 { 105 u32 val; 106 unsigned long interval_mhz = get_internval_val_mhz(); 107 108 if (!interval_mhz) 109 return; 110 111 val = in_le32(DCSR_CGACRE5); 112 writel(val | 0x00000200, DCSR_CGACRE5); 113 114 val = in_le32(EPU_EPCMPR5); 115 writel(interval_mhz, EPU_EPCMPR5); 116 val = in_le32(EPU_EPCCR5); 117 writel(val | 0x82820000, EPU_EPCCR5); 118 val = in_le32(EPU_EPSMCR5); 119 writel(val | 0x002f0000, EPU_EPSMCR5); 120 val = in_le32(EPU_EPECR5); 121 writel(val | 0x20000000, EPU_EPECR5); 122 val = in_le32(EPU_EPGCR); 123 writel(val | 0x80000000, EPU_EPGCR); 124 } 125 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 126 127 static void erratum_rcw_src(void) 128 { 129 #if defined(CONFIG_SPL) 130 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 131 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 132 u32 val; 133 134 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 135 val &= ~DCFG_PORSR1_RCW_SRC; 136 val |= DCFG_PORSR1_RCW_SRC_NOR; 137 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 138 #endif 139 } 140 141 #define I2C_DEBUG_REG 0x6 142 #define I2C_GLITCH_EN 0x8 143 /* 144 * This erratum requires setting glitch_en bit to enable 145 * digital glitch filter to improve clock stability. 146 */ 147 static void erratum_a009203(void) 148 { 149 u8 __iomem *ptr; 150 #ifdef CONFIG_SYS_I2C 151 #ifdef I2C1_BASE_ADDR 152 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 153 154 writeb(I2C_GLITCH_EN, ptr); 155 #endif 156 #ifdef I2C2_BASE_ADDR 157 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 158 159 writeb(I2C_GLITCH_EN, ptr); 160 #endif 161 #ifdef I2C3_BASE_ADDR 162 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 163 164 writeb(I2C_GLITCH_EN, ptr); 165 #endif 166 #ifdef I2C4_BASE_ADDR 167 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 168 169 writeb(I2C_GLITCH_EN, ptr); 170 #endif 171 #endif 172 } 173 void bypass_smmu(void) 174 { 175 u32 val; 176 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 177 out_le32(SMMU_SCR0, val); 178 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 179 out_le32(SMMU_NSCR0, val); 180 } 181 void fsl_lsch3_early_init_f(void) 182 { 183 erratum_rcw_src(); 184 init_early_memctl_regs(); /* tighten IFC timing */ 185 erratum_a009203(); 186 erratum_a008514(); 187 erratum_a008336(); 188 #ifdef CONFIG_CHAIN_OF_TRUST 189 /* In case of Secure Boot, the IBR configures the SMMU 190 * to allow only Secure transactions. 191 * SMMU must be reset in bypass mode. 192 * Set the ClientPD bit and Clear the USFCFG Bit 193 */ 194 if (fsl_check_boot_mode_secure() == 1) 195 bypass_smmu(); 196 #endif 197 } 198 199 #ifdef CONFIG_SCSI_AHCI_PLAT 200 int sata_init(void) 201 { 202 struct ccsr_ahci __iomem *ccsr_ahci; 203 204 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 205 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 206 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 207 208 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 209 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 210 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 211 212 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 213 scsi_scan(0); 214 215 return 0; 216 } 217 #endif 218 219 #elif defined(CONFIG_FSL_LSCH2) 220 #ifdef CONFIG_SCSI_AHCI_PLAT 221 int sata_init(void) 222 { 223 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 224 225 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 226 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 227 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 228 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 229 230 ahci_init((void __iomem *)CONFIG_SYS_SATA); 231 scsi_scan(0); 232 233 return 0; 234 } 235 #endif 236 237 static void erratum_a009929(void) 238 { 239 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 240 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 241 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 242 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 243 244 rstrqmr1 |= 0x00000400; 245 gur_out32(&gur->rstrqmr1, rstrqmr1); 246 writel(0x01000000, dcsr_cop_ccp); 247 #endif 248 } 249 250 /* 251 * This erratum requires setting a value to eddrtqcr1 to optimal 252 * the DDR performance. The eddrtqcr1 register is in SCFG space 253 * of LS1043A and the offset is 0x157_020c. 254 */ 255 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 256 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 257 #error A009660 and A008514 can not be both enabled. 258 #endif 259 260 static void erratum_a009660(void) 261 { 262 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 263 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 264 out_be32(eddrtqcr1, 0x63b20042); 265 #endif 266 } 267 268 static void erratum_a008850_early(void) 269 { 270 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 271 /* part 1 of 2 */ 272 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 273 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 274 275 /* disables propagation of barrier transactions to DDRC from CCI400 */ 276 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 277 278 /* disable the re-ordering in DDRC */ 279 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 280 #endif 281 } 282 283 void erratum_a008850_post(void) 284 { 285 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 286 /* part 2 of 2 */ 287 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 288 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 289 u32 tmp; 290 291 /* enable propagation of barrier transactions to DDRC from CCI400 */ 292 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 293 294 /* enable the re-ordering in DDRC */ 295 tmp = ddr_in32(&ddr->eor); 296 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 297 ddr_out32(&ddr->eor, tmp); 298 #endif 299 } 300 301 void fsl_lsch2_early_init_f(void) 302 { 303 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 304 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 305 306 #ifdef CONFIG_FSL_IFC 307 init_early_memctl_regs(); /* tighten IFC timing */ 308 #endif 309 310 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 311 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 312 #endif 313 /* Make SEC reads and writes snoopable */ 314 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 315 SCFG_SNPCNFGCR_SECWRSNP); 316 317 /* 318 * Enable snoop requests and DVM message requests for 319 * Slave insterface S4 (A53 core cluster) 320 */ 321 out_le32(&cci->slave[4].snoop_ctrl, 322 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 323 324 /* Erratum */ 325 erratum_a008850_early(); /* part 1 of 2 */ 326 erratum_a009929(); 327 erratum_a009660(); 328 } 329 #endif 330 331 #ifdef CONFIG_BOARD_LATE_INIT 332 int board_late_init(void) 333 { 334 #ifdef CONFIG_SCSI_AHCI_PLAT 335 sata_init(); 336 #endif 337 #ifdef CONFIG_CHAIN_OF_TRUST 338 fsl_setenv_chain_of_trust(); 339 #endif 340 341 return 0; 342 } 343 #endif 344