1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/soc.h> 12 #include <asm/io.h> 13 #include <asm/global_data.h> 14 #include <asm/arch-fsl-layerscape/config.h> 15 #ifdef CONFIG_CHAIN_OF_TRUST 16 #include <fsl_validate.h> 17 #endif 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 22 /* 23 * This erratum requires setting a value to eddrtqcr1 to 24 * optimal the DDR performance. 25 */ 26 static void erratum_a008336(void) 27 { 28 u32 *eddrtqcr1; 29 30 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 31 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 32 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 33 out_le32(eddrtqcr1, 0x63b30002); 34 #endif 35 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 36 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 37 out_le32(eddrtqcr1, 0x63b30002); 38 #endif 39 #endif 40 } 41 42 /* 43 * This erratum requires a register write before being Memory 44 * controller 3 being enabled. 45 */ 46 static void erratum_a008514(void) 47 { 48 u32 *eddrtqcr1; 49 50 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 51 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 52 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 53 out_le32(eddrtqcr1, 0x63b20002); 54 #endif 55 #endif 56 } 57 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 58 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 59 60 static unsigned long get_internval_val_mhz(void) 61 { 62 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); 63 /* 64 * interval is the number of platform cycles(MHz) between 65 * wake up events generated by EPU. 66 */ 67 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 68 69 if (interval) 70 interval_mhz = simple_strtoul(interval, NULL, 10); 71 72 return interval_mhz; 73 } 74 75 void erratum_a009635(void) 76 { 77 u32 val; 78 unsigned long interval_mhz = get_internval_val_mhz(); 79 80 if (!interval_mhz) 81 return; 82 83 val = in_le32(DCSR_CGACRE5); 84 writel(val | 0x00000200, DCSR_CGACRE5); 85 86 val = in_le32(EPU_EPCMPR5); 87 writel(interval_mhz, EPU_EPCMPR5); 88 val = in_le32(EPU_EPCCR5); 89 writel(val | 0x82820000, EPU_EPCCR5); 90 val = in_le32(EPU_EPSMCR5); 91 writel(val | 0x002f0000, EPU_EPSMCR5); 92 val = in_le32(EPU_EPECR5); 93 writel(val | 0x20000000, EPU_EPECR5); 94 val = in_le32(EPU_EPGCR); 95 writel(val | 0x80000000, EPU_EPGCR); 96 } 97 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 98 99 static void erratum_a008751(void) 100 { 101 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 102 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 103 104 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); 105 #endif 106 } 107 108 static void erratum_rcw_src(void) 109 { 110 #if defined(CONFIG_SPL) 111 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 112 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 113 u32 val; 114 115 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 116 val &= ~DCFG_PORSR1_RCW_SRC; 117 val |= DCFG_PORSR1_RCW_SRC_NOR; 118 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 119 #endif 120 } 121 122 #define I2C_DEBUG_REG 0x6 123 #define I2C_GLITCH_EN 0x8 124 /* 125 * This erratum requires setting glitch_en bit to enable 126 * digital glitch filter to improve clock stability. 127 */ 128 static void erratum_a009203(void) 129 { 130 u8 __iomem *ptr; 131 #ifdef CONFIG_SYS_I2C 132 #ifdef I2C1_BASE_ADDR 133 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 134 135 writeb(I2C_GLITCH_EN, ptr); 136 #endif 137 #ifdef I2C2_BASE_ADDR 138 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 139 140 writeb(I2C_GLITCH_EN, ptr); 141 #endif 142 #ifdef I2C3_BASE_ADDR 143 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 144 145 writeb(I2C_GLITCH_EN, ptr); 146 #endif 147 #ifdef I2C4_BASE_ADDR 148 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 149 150 writeb(I2C_GLITCH_EN, ptr); 151 #endif 152 #endif 153 } 154 void bypass_smmu(void) 155 { 156 u32 val; 157 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 158 out_le32(SMMU_SCR0, val); 159 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 160 out_le32(SMMU_NSCR0, val); 161 } 162 void fsl_lsch3_early_init_f(void) 163 { 164 erratum_a008751(); 165 erratum_rcw_src(); 166 init_early_memctl_regs(); /* tighten IFC timing */ 167 erratum_a009203(); 168 erratum_a008514(); 169 erratum_a008336(); 170 #ifdef CONFIG_CHAIN_OF_TRUST 171 /* In case of Secure Boot, the IBR configures the SMMU 172 * to allow only Secure transactions. 173 * SMMU must be reset in bypass mode. 174 * Set the ClientPD bit and Clear the USFCFG Bit 175 */ 176 if (fsl_check_boot_mode_secure() == 1) 177 bypass_smmu(); 178 #endif 179 } 180 181 #ifdef CONFIG_SCSI_AHCI_PLAT 182 int sata_init(void) 183 { 184 struct ccsr_ahci __iomem *ccsr_ahci; 185 186 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 187 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 188 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 189 190 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 191 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 192 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 193 194 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 195 scsi_scan(0); 196 197 return 0; 198 } 199 #endif 200 201 #elif defined(CONFIG_LS1043A) 202 #ifdef CONFIG_SCSI_AHCI_PLAT 203 int sata_init(void) 204 { 205 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 206 207 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 208 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 209 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 210 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 211 212 ahci_init((void __iomem *)CONFIG_SYS_SATA); 213 scsi_scan(0); 214 215 return 0; 216 } 217 #endif 218 219 static void erratum_a009929(void) 220 { 221 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 222 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 223 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 224 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 225 226 rstrqmr1 |= 0x00000400; 227 gur_out32(&gur->rstrqmr1, rstrqmr1); 228 writel(0x01000000, dcsr_cop_ccp); 229 #endif 230 } 231 232 /* 233 * This erratum requires setting a value to eddrtqcr1 to optimal 234 * the DDR performance. The eddrtqcr1 register is in SCFG space 235 * of LS1043A and the offset is 0x157_020c. 236 */ 237 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 238 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 239 #error A009660 and A008514 can not be both enabled. 240 #endif 241 242 static void erratum_a009660(void) 243 { 244 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 245 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 246 out_be32(eddrtqcr1, 0x63b20042); 247 #endif 248 } 249 250 void fsl_lsch2_early_init_f(void) 251 { 252 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 253 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 254 255 #ifdef CONFIG_FSL_IFC 256 init_early_memctl_regs(); /* tighten IFC timing */ 257 #endif 258 259 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 260 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 261 #endif 262 /* Make SEC reads and writes snoopable */ 263 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 264 SCFG_SNPCNFGCR_SECWRSNP); 265 266 /* 267 * Enable snoop requests and DVM message requests for 268 * Slave insterface S4 (A53 core cluster) 269 */ 270 out_le32(&cci->slave[4].snoop_ctrl, 271 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 272 273 /* Erratum */ 274 erratum_a009929(); 275 erratum_a009660(); 276 } 277 #endif 278 279 #ifdef CONFIG_BOARD_LATE_INIT 280 int board_late_init(void) 281 { 282 #ifdef CONFIG_SCSI_AHCI_PLAT 283 sata_init(); 284 #endif 285 #ifdef CONFIG_CHAIN_OF_TRUST 286 fsl_setenv_chain_of_trust(); 287 #endif 288 289 return 0; 290 } 291 #endif 292