1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ifc.h> 9 #include <asm/arch/soc.h> 10 #include <asm/io.h> 11 #include <asm/global_data.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_LS2085A 16 static void erratum_a008751(void) 17 { 18 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 19 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 20 21 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); 22 #endif 23 } 24 25 static void erratum_rcw_src(void) 26 { 27 #if defined(CONFIG_SPL) 28 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 29 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 30 u32 val; 31 32 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 33 val &= ~DCFG_PORSR1_RCW_SRC; 34 val |= DCFG_PORSR1_RCW_SRC_NOR; 35 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 36 #endif 37 } 38 39 #define I2C_DEBUG_REG 0x6 40 #define I2C_GLITCH_EN 0x8 41 /* 42 * This erratum requires setting glitch_en bit to enable 43 * digital glitch filter to improve clock stability. 44 */ 45 static void erratum_a009203(void) 46 { 47 u8 __iomem *ptr; 48 #ifdef CONFIG_SYS_I2C 49 #ifdef I2C1_BASE_ADDR 50 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 51 52 writeb(I2C_GLITCH_EN, ptr); 53 #endif 54 #ifdef I2C2_BASE_ADDR 55 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 56 57 writeb(I2C_GLITCH_EN, ptr); 58 #endif 59 #ifdef I2C3_BASE_ADDR 60 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 61 62 writeb(I2C_GLITCH_EN, ptr); 63 #endif 64 #ifdef I2C4_BASE_ADDR 65 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 66 67 writeb(I2C_GLITCH_EN, ptr); 68 #endif 69 #endif 70 } 71 72 void fsl_lsch3_early_init_f(void) 73 { 74 erratum_a008751(); 75 erratum_rcw_src(); 76 init_early_memctl_regs(); /* tighten IFC timing */ 77 erratum_a009203(); 78 } 79 80 #elif defined(CONFIG_LS1043A) 81 void fsl_lsch2_early_init_f(void) 82 { 83 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 84 85 #ifdef CONFIG_FSL_IFC 86 init_early_memctl_regs(); /* tighten IFC timing */ 87 #endif 88 89 /* 90 * Enable snoop requests and DVM message requests for 91 * Slave insterface S4 (A53 core cluster) 92 */ 93 out_le32(&cci->slave[4].snoop_ctrl, 94 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 95 } 96 #endif 97 98 #ifdef CONFIG_BOARD_LATE_INIT 99 int board_late_init(void) 100 { 101 return 0; 102 } 103 #endif 104