1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/system.h> 10 #include <asm/arch/mp.h> 11 #include <asm/arch/soc.h> 12 #include "cpu.h" 13 #include <asm/arch-fsl-layerscape/soc.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 void *get_spin_tbl_addr(void) 18 { 19 return &__spin_table; 20 } 21 22 phys_addr_t determine_mp_bootpg(void) 23 { 24 return (phys_addr_t)&secondary_boot_code; 25 } 26 27 void update_os_arch_secondary_cores(uint8_t os_arch) 28 { 29 u64 *table = get_spin_tbl_addr(); 30 int i; 31 32 for (i = 1; i < CONFIG_MAX_CPUS; i++) 33 table[i * WORDS_PER_SPIN_TABLE_ENTRY + 34 SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch; 35 } 36 37 #ifdef CONFIG_FSL_LSCH3 38 void wake_secondary_core_n(int cluster, int core, int cluster_cores) 39 { 40 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 41 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); 42 u32 mpidr = 0; 43 44 mpidr = ((cluster << 8) | core); 45 /* 46 * mpidr_el1 register value of core which needs to be released 47 * is written to scratchrw[6] register 48 */ 49 gur_out32(&gur->scratchrw[6], mpidr); 50 asm volatile("dsb st" : : : "memory"); 51 rst->brrl |= 1 << ((cluster * cluster_cores) + core); 52 asm volatile("dsb st" : : : "memory"); 53 /* 54 * scratchrw[6] register value is polled 55 * when the value becomes zero, this means that this core is up 56 * and running, next core can be released now 57 */ 58 while (gur_in32(&gur->scratchrw[6]) != 0) 59 ; 60 } 61 #endif 62 63 int fsl_layerscape_wake_seconday_cores(void) 64 { 65 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 66 #ifdef CONFIG_FSL_LSCH3 67 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); 68 u32 svr, ver, cluster, type; 69 int j = 0, cluster_cores = 0; 70 #elif defined(CONFIG_FSL_LSCH2) 71 struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); 72 #endif 73 u32 cores, cpu_up_mask = 1; 74 int i, timeout = 10; 75 u64 *table = get_spin_tbl_addr(); 76 77 #ifdef COUNTER_FREQUENCY_REAL 78 /* update for secondary cores */ 79 __real_cntfrq = COUNTER_FREQUENCY_REAL; 80 flush_dcache_range((unsigned long)&__real_cntfrq, 81 (unsigned long)&__real_cntfrq + 8); 82 #endif 83 84 cores = cpu_mask(); 85 /* Clear spin table so that secondary processors 86 * observe the correct value after waking up from wfe. 87 */ 88 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); 89 flush_dcache_range((unsigned long)table, 90 (unsigned long)table + 91 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); 92 93 printf("Waking secondary cores to start from %lx\n", gd->relocaddr); 94 95 #ifdef CONFIG_FSL_LSCH3 96 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); 97 gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); 98 99 svr = gur_in32(&gur->svr); 100 ver = SVR_SOC_VER(svr); 101 if (ver == SVR_LS2080A || ver == SVR_LS2085A) { 102 gur_out32(&gur->scratchrw[6], 1); 103 asm volatile("dsb st" : : : "memory"); 104 rst->brrl = cores; 105 asm volatile("dsb st" : : : "memory"); 106 } else { 107 /* 108 * Release the cores out of reset one-at-a-time to avoid 109 * power spikes 110 */ 111 i = 0; 112 cluster = in_le32(&gur->tp_cluster[i].lower); 113 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 114 type = initiator_type(cluster, j); 115 if (type && 116 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 117 cluster_cores++; 118 } 119 120 do { 121 cluster = in_le32(&gur->tp_cluster[i].lower); 122 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 123 type = initiator_type(cluster, j); 124 if (type && 125 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 126 wake_secondary_core_n(i, j, 127 cluster_cores); 128 } 129 i++; 130 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 131 } 132 #elif defined(CONFIG_FSL_LSCH2) 133 scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); 134 scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); 135 asm volatile("dsb st" : : : "memory"); 136 gur_out32(&gur->brrl, cores); 137 asm volatile("dsb st" : : : "memory"); 138 139 /* Bootup online cores */ 140 scfg_out32(&scfg->corebcr, cores); 141 #endif 142 /* This is needed as a precautionary measure. 143 * If some code before this has accidentally released the secondary 144 * cores then the pre-bootloader code will trap them in a "wfe" unless 145 * the scratchrw[6] is set. In this case we need a sev here to get these 146 * cores moving again. 147 */ 148 asm volatile("sev"); 149 150 while (timeout--) { 151 flush_dcache_range((unsigned long)table, (unsigned long)table + 152 CONFIG_MAX_CPUS * 64); 153 for (i = 1; i < CONFIG_MAX_CPUS; i++) { 154 if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + 155 SPIN_TABLE_ELEM_STATUS_IDX]) 156 cpu_up_mask |= 1 << i; 157 } 158 if (hweight32(cpu_up_mask) == hweight32(cores)) 159 break; 160 udelay(10); 161 } 162 if (timeout <= 0) { 163 printf("Not all cores (0x%x) are up (0x%x)\n", 164 cores, cpu_up_mask); 165 return 1; 166 } 167 printf("All (%d) cores are up.\n", hweight32(cores)); 168 169 return 0; 170 } 171 172 int is_core_valid(unsigned int core) 173 { 174 return !!((1 << core) & cpu_mask()); 175 } 176 177 static int is_pos_valid(unsigned int pos) 178 { 179 return !!((1 << pos) & cpu_pos_mask()); 180 } 181 182 int is_core_online(u64 cpu_id) 183 { 184 u64 *table; 185 int pos = id_to_core(cpu_id); 186 table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; 187 return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; 188 } 189 190 int cpu_reset(int nr) 191 { 192 puts("Feature is not implemented.\n"); 193 194 return 0; 195 } 196 197 int cpu_disable(int nr) 198 { 199 puts("Feature is not implemented.\n"); 200 201 return 0; 202 } 203 204 static int core_to_pos(int nr) 205 { 206 u32 cores = cpu_pos_mask(); 207 int i, count = 0; 208 209 if (nr == 0) { 210 return 0; 211 } else if (nr >= hweight32(cores)) { 212 puts("Not a valid core number.\n"); 213 return -1; 214 } 215 216 for (i = 1; i < 32; i++) { 217 if (is_pos_valid(i)) { 218 count++; 219 if (count == nr) 220 break; 221 } 222 } 223 224 if (count != nr) 225 return -1; 226 227 return i; 228 } 229 230 int cpu_status(int nr) 231 { 232 u64 *table; 233 int pos; 234 235 if (nr == 0) { 236 table = (u64 *)get_spin_tbl_addr(); 237 printf("table base @ 0x%p\n", table); 238 } else { 239 pos = core_to_pos(nr); 240 if (pos < 0) 241 return -1; 242 table = (u64 *)get_spin_tbl_addr() + pos * 243 WORDS_PER_SPIN_TABLE_ENTRY; 244 printf("table @ 0x%p\n", table); 245 printf(" addr - 0x%016llx\n", 246 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); 247 printf(" status - 0x%016llx\n", 248 table[SPIN_TABLE_ELEM_STATUS_IDX]); 249 printf(" lpid - 0x%016llx\n", 250 table[SPIN_TABLE_ELEM_LPID_IDX]); 251 } 252 253 return 0; 254 } 255 256 int cpu_release(int nr, int argc, char * const argv[]) 257 { 258 u64 boot_addr; 259 u64 *table = (u64 *)get_spin_tbl_addr(); 260 int pos; 261 262 pos = core_to_pos(nr); 263 if (pos <= 0) 264 return -1; 265 266 table += pos * WORDS_PER_SPIN_TABLE_ENTRY; 267 boot_addr = simple_strtoull(argv[0], NULL, 16); 268 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; 269 flush_dcache_range((unsigned long)table, 270 (unsigned long)table + SPIN_TABLE_ELEM_SIZE); 271 asm volatile("dsb st"); 272 smp_kick_all_cpus(); /* only those with entry addr set will run */ 273 /* 274 * When the first release command runs, all cores are set to go. Those 275 * without a valid entry address will be trapped by "wfe". "sev" kicks 276 * them off to check the address again. When set, they continue to run. 277 */ 278 asm volatile("sev"); 279 280 return 0; 281 } 282