1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/fsl_serdes.h> 9 10 struct serdes_config { 11 u8 protocol; 12 u8 lanes[SRDS_MAX_LANES]; 13 }; 14 15 static struct serdes_config serdes1_cfg_tbl[] = { 16 /* SerDes 1 */ 17 {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, 18 {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, 19 {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 20 SGMII1 } }, 21 {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 22 SGMII1 } }, 23 {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 24 SGMII1 } }, 25 {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 26 SGMII1 } }, 27 {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 28 SGMII1 } }, 29 {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, 30 {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, 31 #ifdef CONFIG_LS2080A 32 {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, 33 #endif 34 #ifdef CONFIG_LS2085A 35 {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, 36 #endif 37 {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, 38 {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, 39 {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, 40 QSGMII_B} }, 41 {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, 42 {} 43 }; 44 static struct serdes_config serdes2_cfg_tbl[] = { 45 /* SerDes 2 */ 46 {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 47 SGMII16 } }, 48 {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 49 SGMII16 } }, 50 {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 51 SGMII16 } }, 52 {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 53 SGMII16 } }, 54 {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 55 SGMII16 } }, 56 {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 57 {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 58 {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 59 {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 60 {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 61 {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 62 {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 63 {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 64 {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, 65 SGMII16 } }, 66 {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, 67 PCIE4 } }, 68 {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 69 SATA2 } }, 70 {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 71 SATA2 } }, 72 {} 73 }; 74 75 static struct serdes_config *serdes_cfg_tbl[] = { 76 serdes1_cfg_tbl, 77 serdes2_cfg_tbl, 78 }; 79 80 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 81 { 82 struct serdes_config *ptr; 83 84 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 85 return 0; 86 87 ptr = serdes_cfg_tbl[serdes]; 88 while (ptr->protocol) { 89 if (ptr->protocol == cfg) 90 return ptr->lanes[lane]; 91 ptr++; 92 } 93 94 return 0; 95 } 96 97 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 98 { 99 int i; 100 struct serdes_config *ptr; 101 102 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 103 return 0; 104 105 ptr = serdes_cfg_tbl[serdes]; 106 while (ptr->protocol) { 107 if (ptr->protocol == prtcl) 108 break; 109 ptr++; 110 } 111 112 if (!ptr->protocol) 113 return 0; 114 115 for (i = 0; i < SRDS_MAX_LANES; i++) { 116 if (ptr->lanes[i] != NONE) 117 return 1; 118 } 119 120 return 0; 121 } 122