1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/fsl_serdes.h> 9 10 struct serdes_config { 11 u8 protocol; 12 u8 lanes[SRDS_MAX_LANES]; 13 }; 14 15 static struct serdes_config serdes1_cfg_tbl[] = { 16 /* SerDes 1 */ 17 {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, 18 {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, 19 {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 20 SGMII1 } }, 21 {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 22 SGMII1 } }, 23 {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 24 SGMII1 } }, 25 {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 26 SGMII1 } }, 27 {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 28 SGMII1 } }, 29 {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, 30 {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, 31 {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, 32 {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, 33 {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, 34 {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, 35 QSGMII_A} }, 36 {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, 37 {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2, 38 PCIE1 } }, 39 {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, 40 {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } }, 41 {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } }, 42 {} 43 }; 44 static struct serdes_config serdes2_cfg_tbl[] = { 45 /* SerDes 2 */ 46 {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 47 SGMII16 } }, 48 {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 49 SGMII16 } }, 50 {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 51 SGMII16 } }, 52 {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 53 SGMII16 } }, 54 {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 55 SGMII16 } }, 56 {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 57 {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 58 {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 59 {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 60 {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 61 {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 62 {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 63 {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 64 {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, 65 PCIE4 } }, 66 {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, 67 SGMII16 } }, 68 {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 69 SATA2 } }, 70 {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 71 SATA2 } }, 72 {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } }, 73 {} 74 }; 75 76 static struct serdes_config *serdes_cfg_tbl[] = { 77 serdes1_cfg_tbl, 78 serdes2_cfg_tbl, 79 }; 80 81 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 82 { 83 struct serdes_config *ptr; 84 85 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 86 return 0; 87 88 ptr = serdes_cfg_tbl[serdes]; 89 while (ptr->protocol) { 90 if (ptr->protocol == cfg) 91 return ptr->lanes[lane]; 92 ptr++; 93 } 94 95 return 0; 96 } 97 98 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 99 { 100 int i; 101 struct serdes_config *ptr; 102 103 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 104 return 0; 105 106 ptr = serdes_cfg_tbl[serdes]; 107 while (ptr->protocol) { 108 if (ptr->protocol == prtcl) 109 break; 110 ptr++; 111 } 112 113 if (!ptr->protocol) 114 return 0; 115 116 for (i = 0; i < SRDS_MAX_LANES; i++) { 117 if (ptr->lanes[i] != NONE) 118 return 1; 119 } 120 121 return 0; 122 } 123