1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/fsl_serdes.h> 9 10 struct serdes_config { 11 u8 protocol; 12 u8 lanes[SRDS_MAX_LANES]; 13 }; 14 15 static struct serdes_config serdes1_cfg_tbl[] = { 16 /* SerDes 1 */ 17 {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, 18 {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, 19 {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 20 SGMII1 } }, 21 {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 22 SGMII1 } }, 23 {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 24 SGMII1 } }, 25 {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 26 SGMII1 } }, 27 {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, 28 SGMII1 } }, 29 {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, 30 {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, 31 {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, 32 {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, 33 {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, 34 {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, 35 QSGMII_B} }, 36 {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, 37 {} 38 }; 39 static struct serdes_config serdes2_cfg_tbl[] = { 40 /* SerDes 2 */ 41 {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 42 SGMII16 } }, 43 {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 44 SGMII16 } }, 45 {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 46 SGMII16 } }, 47 {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 48 SGMII16 } }, 49 {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, 50 SGMII16 } }, 51 {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 52 {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, 53 {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 54 {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, 55 {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 56 {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, 57 {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 58 {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, 59 {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, 60 SGMII16 } }, 61 {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, 62 PCIE4 } }, 63 {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 64 SATA2 } }, 65 {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, 66 SATA2 } }, 67 {} 68 }; 69 70 static struct serdes_config *serdes_cfg_tbl[] = { 71 serdes1_cfg_tbl, 72 serdes2_cfg_tbl, 73 }; 74 75 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 76 { 77 struct serdes_config *ptr; 78 79 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 80 return 0; 81 82 ptr = serdes_cfg_tbl[serdes]; 83 while (ptr->protocol) { 84 if (ptr->protocol == cfg) 85 return ptr->lanes[lane]; 86 ptr++; 87 } 88 89 return 0; 90 } 91 92 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 93 { 94 int i; 95 struct serdes_config *ptr; 96 97 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 98 return 0; 99 100 ptr = serdes_cfg_tbl[serdes]; 101 while (ptr->protocol) { 102 if (ptr->protocol == prtcl) 103 break; 104 ptr++; 105 } 106 107 if (!ptr->protocol) 108 return 0; 109 110 for (i = 0; i < SRDS_MAX_LANES; i++) { 111 if (ptr->lanes[i] != NONE) 112 return 1; 113 } 114 115 return 0; 116 } 117