1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <linux/errno.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <asm/arch/soc.h> 12 #include <fsl-mc/ldpaa_wriop.h> 13 14 #ifdef CONFIG_SYS_FSL_SRDS_1 15 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; 16 #endif 17 #ifdef CONFIG_SYS_FSL_SRDS_2 18 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; 19 #endif 20 21 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 22 int xfi_dpmac[XFI8 + 1]; 23 int sgmii_dpmac[SGMII16 + 1]; 24 #endif 25 26 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) 27 { 28 return; 29 } 30 31 int is_serdes_configured(enum srds_prtcl device) 32 { 33 int ret = 0; 34 35 #ifdef CONFIG_SYS_FSL_SRDS_1 36 if (!serdes1_prtcl_map[NONE]) 37 fsl_serdes_init(); 38 39 ret |= serdes1_prtcl_map[device]; 40 #endif 41 #ifdef CONFIG_SYS_FSL_SRDS_2 42 if (!serdes2_prtcl_map[NONE]) 43 fsl_serdes_init(); 44 45 ret |= serdes2_prtcl_map[device]; 46 #endif 47 48 return !!ret; 49 } 50 51 int serdes_get_first_lane(u32 sd, enum srds_prtcl device) 52 { 53 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 54 u32 cfg = 0; 55 int i; 56 57 switch (sd) { 58 #ifdef CONFIG_SYS_FSL_SRDS_1 59 case FSL_SRDS_1: 60 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); 61 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK; 62 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; 63 break; 64 #endif 65 #ifdef CONFIG_SYS_FSL_SRDS_2 66 case FSL_SRDS_2: 67 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); 68 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; 69 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; 70 break; 71 #endif 72 default: 73 printf("invalid SerDes%d\n", sd); 74 break; 75 } 76 /* Is serdes enabled at all? */ 77 if (cfg == 0) 78 return -ENODEV; 79 80 for (i = 0; i < SRDS_MAX_LANES; i++) { 81 if (serdes_get_prtcl(sd, cfg, i) == device) 82 return i; 83 } 84 85 return -ENODEV; 86 } 87 88 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, 89 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) 90 { 91 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 92 u32 cfg; 93 int lane; 94 95 if (serdes_prtcl_map[NONE]) 96 return; 97 98 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); 99 100 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; 101 cfg >>= sd_prctl_shift; 102 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); 103 104 if (!is_serdes_prtcl_valid(sd, cfg)) 105 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); 106 107 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 108 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); 109 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) 110 debug("Unknown SerDes lane protocol %d\n", lane_prtcl); 111 else { 112 serdes_prtcl_map[lane_prtcl] = 1; 113 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 114 switch (lane_prtcl) { 115 case QSGMII_A: 116 case QSGMII_B: 117 case QSGMII_C: 118 case QSGMII_D: 119 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl); 120 break; 121 default: 122 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) 123 wriop_init_dpmac(sd, 124 xfi_dpmac[lane_prtcl], 125 (int)lane_prtcl); 126 127 if (lane_prtcl >= SGMII1 && 128 lane_prtcl <= SGMII16) 129 wriop_init_dpmac(sd, sgmii_dpmac[ 130 lane_prtcl], 131 (int)lane_prtcl); 132 break; 133 } 134 #endif 135 } 136 } 137 138 /* Set the first element to indicate serdes has been initialized */ 139 serdes_prtcl_map[NONE] = 1; 140 } 141 142 void fsl_serdes_init(void) 143 { 144 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 145 int i , j; 146 147 for (i = XFI1, j = 1; i <= XFI8; i++, j++) 148 xfi_dpmac[i] = j; 149 150 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) 151 sgmii_dpmac[i] = j; 152 #endif 153 154 #ifdef CONFIG_SYS_FSL_SRDS_1 155 serdes_init(FSL_SRDS_1, 156 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, 157 FSL_CHASSIS3_SRDS1_REGSR, 158 FSL_CHASSIS3_SRDS1_PRTCL_MASK, 159 FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, 160 serdes1_prtcl_map); 161 #endif 162 #ifdef CONFIG_SYS_FSL_SRDS_2 163 serdes_init(FSL_SRDS_2, 164 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, 165 FSL_CHASSIS3_SRDS2_REGSR, 166 FSL_CHASSIS3_SRDS2_PRTCL_MASK, 167 FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, 168 serdes2_prtcl_map); 169 #endif 170 } 171