1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <linux/errno.h>
9 #include <asm/arch/fsl_serdes.h>
10 #include <asm/arch/soc.h>
11 #include <fsl-mc/ldpaa_wriop.h>
12 
13 #ifdef CONFIG_SYS_FSL_SRDS_1
14 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
15 #endif
16 #ifdef CONFIG_SYS_FSL_SRDS_2
17 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
18 #endif
19 
20 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
21 int xfi_dpmac[XFI8 + 1];
22 int sgmii_dpmac[SGMII16 + 1];
23 #endif
24 
25 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
26 {
27 	return;
28 }
29 
30 /*
31  *The return value of this func is the serdes protocol used.
32  *Typically this function is called number of times depending
33  *upon the number of serdes blocks in the Silicon.
34  *Zero is used to denote that no serdes was enabled,
35  *this is the case when golden RCW was used where DPAA2 bring was
36  *intentionally removed to achieve boot to prompt
37 */
38 
39 __weak int serdes_get_number(int serdes, int cfg)
40 {
41 	return cfg;
42 }
43 
44 int is_serdes_configured(enum srds_prtcl device)
45 {
46 	int ret = 0;
47 
48 #ifdef CONFIG_SYS_FSL_SRDS_1
49 	if (!serdes1_prtcl_map[NONE])
50 		fsl_serdes_init();
51 
52 	ret |= serdes1_prtcl_map[device];
53 #endif
54 #ifdef CONFIG_SYS_FSL_SRDS_2
55 	if (!serdes2_prtcl_map[NONE])
56 		fsl_serdes_init();
57 
58 	ret |= serdes2_prtcl_map[device];
59 #endif
60 
61 	return !!ret;
62 }
63 
64 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
65 {
66 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
67 	u32 cfg = 0;
68 	int i;
69 
70 	switch (sd) {
71 #ifdef CONFIG_SYS_FSL_SRDS_1
72 	case FSL_SRDS_1:
73 		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
74 		cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
75 		cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
76 		break;
77 #endif
78 #ifdef CONFIG_SYS_FSL_SRDS_2
79 	case FSL_SRDS_2:
80 		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
81 		cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
82 		cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
83 		break;
84 #endif
85 	default:
86 		printf("invalid SerDes%d\n", sd);
87 		break;
88 	}
89 
90 	cfg = serdes_get_number(sd, cfg);
91 
92 	/* Is serdes enabled at all? */
93 	if (cfg == 0)
94 		return -ENODEV;
95 
96 	for (i = 0; i < SRDS_MAX_LANES; i++) {
97 		if (serdes_get_prtcl(sd, cfg, i) == device)
98 			return i;
99 	}
100 
101 	return -ENODEV;
102 }
103 
104 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
105 		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
106 {
107 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
108 	u32 cfg;
109 	int lane;
110 
111 	if (serdes_prtcl_map[NONE])
112 		return;
113 
114 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
115 
116 	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
117 	cfg >>= sd_prctl_shift;
118 
119 	cfg = serdes_get_number(sd, cfg);
120 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
121 
122 	if (!is_serdes_prtcl_valid(sd, cfg))
123 		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
124 
125 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
126 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
127 		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
128 			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
129 		else {
130 			serdes_prtcl_map[lane_prtcl] = 1;
131 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
132 			switch (lane_prtcl) {
133 			case QSGMII_A:
134 			case QSGMII_B:
135 			case QSGMII_C:
136 			case QSGMII_D:
137 				wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
138 				break;
139 			default:
140 				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
141 					wriop_init_dpmac(sd,
142 							 xfi_dpmac[lane_prtcl],
143 							 (int)lane_prtcl);
144 
145 				 if (lane_prtcl >= SGMII1 &&
146 				     lane_prtcl <= SGMII16)
147 					wriop_init_dpmac(sd, sgmii_dpmac[
148 							 lane_prtcl],
149 							 (int)lane_prtcl);
150 				break;
151 			}
152 #endif
153 		}
154 	}
155 
156 	/* Set the first element to indicate serdes has been initialized */
157 	serdes_prtcl_map[NONE] = 1;
158 }
159 
160 __weak int get_serdes_volt(void)
161 {
162 	return -1;
163 }
164 
165 __weak int set_serdes_volt(int svdd)
166 {
167 	return -1;
168 }
169 
170 #define LNAGCR0_RT_RSTB		0x00600000
171 
172 #define RSTCTL_RESET_MASK	0x000000E0
173 
174 #define RSTCTL_RSTREQ		0x80000000
175 #define RSTCTL_RST_DONE		0x40000000
176 #define RSTCTL_RSTERR		0x20000000
177 
178 #define RSTCTL_SDEN		0x00000020
179 #define RSTCTL_SDRST_B		0x00000040
180 #define RSTCTL_PLLRST_B		0x00000080
181 
182 #define TCALCR_CALRST_B		0x08000000
183 
184 struct serdes_prctl_info {
185 	u32 id;
186 	u32 mask;
187 	u32 shift;
188 };
189 
190 struct serdes_prctl_info srds_prctl_info[] = {
191 #ifdef CONFIG_SYS_FSL_SRDS_1
192 	{.id = 1,
193 	 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
194 	 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
195 	},
196 
197 #endif
198 #ifdef CONFIG_SYS_FSL_SRDS_2
199 	{.id = 2,
200 	 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
201 	 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
202 	},
203 #endif
204 	{} /* NULL ENTRY */
205 };
206 
207 static int get_serdes_prctl_info_idx(u32 serdes_id)
208 {
209 	int pos = 0;
210 	struct serdes_prctl_info *srds_info;
211 
212 	/* loop until NULL ENTRY defined by .id=0 */
213 	for (srds_info = srds_prctl_info; srds_info->id != 0;
214 	     srds_info++, pos++) {
215 		if (srds_info->id == serdes_id)
216 			return pos;
217 	}
218 
219 	return -1;
220 }
221 
222 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
223 				   struct ccsr_serdes __iomem *serdes_base,
224 				   bool cmplt)
225 {
226 	int i, pos;
227 	u32 cfg_tmp;
228 
229 	pos = get_serdes_prctl_info_idx(serdes_id);
230 	if (pos == -1) {
231 		printf("invalid serdes_id %d\n", serdes_id);
232 		return;
233 	}
234 
235 	cfg_tmp = cfg & srds_prctl_info[pos].mask;
236 	cfg_tmp >>= srds_prctl_info[pos].shift;
237 
238 	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
239 		if (cmplt)
240 			setbits_le32(&serdes_base->lane[i].gcr0,
241 				     LNAGCR0_RT_RSTB);
242 		else
243 			clrbits_le32(&serdes_base->lane[i].gcr0,
244 				     LNAGCR0_RT_RSTB);
245 	}
246 }
247 
248 static void do_pll_reset(u32 cfg,
249 			 struct ccsr_serdes __iomem *serdes_base)
250 {
251 	int i;
252 
253 	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
254 		clrbits_le32(&serdes_base->bank[i].rstctl,
255 			     RSTCTL_RESET_MASK);
256 		udelay(1);
257 
258 		setbits_le32(&serdes_base->bank[i].rstctl,
259 			     RSTCTL_RSTREQ);
260 	}
261 	udelay(1);
262 }
263 
264 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
265 {
266 	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
267 	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
268 }
269 
270 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
271 				    struct ccsr_serdes __iomem *serdes_base)
272 {
273 	if (!(cfg == 0x3 && i == 1)) {
274 		udelay(1);
275 		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
276 		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
277 	}
278 	udelay(1);
279 }
280 
281 static void do_pll_reset_done(u32 cfg,
282 			      struct ccsr_serdes __iomem *serdes_base)
283 {
284 	int i;
285 	u32 reg = 0;
286 
287 	for (i = 0; i < 2; i++) {
288 		reg = in_le32(&serdes_base->bank[i].pllcr0);
289 		if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
290 			setbits_le32(&serdes_base->bank[i].rstctl,
291 				     RSTCTL_RST_DONE);
292 		}
293 	}
294 }
295 
296 static void do_serdes_enable(u32 cfg,
297 			     struct ccsr_serdes __iomem *serdes_base)
298 {
299 	int i;
300 
301 	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
302 		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
303 		udelay(1);
304 
305 		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
306 		udelay(1);
307 		/* Take the Rx/Tx calibration out of reset */
308 		do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
309 	}
310 }
311 
312 static void do_pll_lock(u32 cfg,
313 			struct ccsr_serdes __iomem *serdes_base)
314 {
315 	int i;
316 	u32 reg = 0;
317 
318 	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
319 		/* if the PLL is not locked, set RST_ERR */
320 		reg = in_le32(&serdes_base->bank[i].pllcr0);
321 		if (!((reg >> 23) & 0x1)) {
322 			setbits_le32(&serdes_base->bank[i].rstctl,
323 				     RSTCTL_RSTERR);
324 		} else {
325 			udelay(1);
326 			setbits_le32(&serdes_base->bank[i].rstctl,
327 				     RSTCTL_SDRST_B);
328 			udelay(1);
329 		}
330 	}
331 }
332 
333 int setup_serdes_volt(u32 svdd)
334 {
335 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
336 	struct ccsr_serdes __iomem *serdes1_base =
337 			(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
338 	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
339 #ifdef CONFIG_SYS_FSL_SRDS_2
340 	struct ccsr_serdes __iomem *serdes2_base =
341 			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
342 	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
343 #endif
344 	u32 cfg_tmp;
345 	int svdd_cur, svdd_tar;
346 	int ret = 1;
347 
348 	/* Only support switch SVDD to 900mV */
349 	if (svdd != 900)
350 		return -EINVAL;
351 
352 	/* Scale up to the LTC resolution is 1/4096V */
353 	svdd = (svdd * 4096) / 1000;
354 
355 	svdd_tar = svdd;
356 	svdd_cur = get_serdes_volt();
357 	if (svdd_cur < 0)
358 		return -EINVAL;
359 
360 	debug("%s: current SVDD: %x; target SVDD: %x\n",
361 	      __func__, svdd_cur, svdd_tar);
362 	if (svdd_cur == svdd_tar)
363 		return 0;
364 
365 	/* Put the all enabled lanes in reset */
366 #ifdef CONFIG_SYS_FSL_SRDS_1
367 	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
368 #endif
369 
370 #ifdef CONFIG_SYS_FSL_SRDS_2
371 	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
372 #endif
373 
374 	/* Put the all enabled PLL in reset */
375 #ifdef CONFIG_SYS_FSL_SRDS_1
376 	cfg_tmp = cfg_rcwsrds1 & 0x3;
377 	do_pll_reset(cfg_tmp, serdes1_base);
378 #endif
379 
380 #ifdef CONFIG_SYS_FSL_SRDS_2
381 	cfg_tmp = cfg_rcwsrds1 & 0xC;
382 	cfg_tmp >>= 2;
383 	do_pll_reset(cfg_tmp, serdes2_base);
384 #endif
385 
386 	/* Put the Rx/Tx calibration into reset */
387 #ifdef CONFIG_SYS_FSL_SRDS_1
388 	do_rx_tx_cal_reset(serdes1_base);
389 #endif
390 
391 #ifdef CONFIG_SYS_FSL_SRDS_2
392 	do_rx_tx_cal_reset(serdes2_base);
393 #endif
394 
395 	ret = set_serdes_volt(svdd);
396 	if (ret < 0) {
397 		printf("could not change SVDD\n");
398 		ret = -1;
399 	}
400 
401 	/* For each PLL that’s not disabled via RCW enable the SERDES */
402 #ifdef CONFIG_SYS_FSL_SRDS_1
403 	cfg_tmp = cfg_rcwsrds1 & 0x3;
404 	do_serdes_enable(cfg_tmp, serdes1_base);
405 #endif
406 #ifdef CONFIG_SYS_FSL_SRDS_2
407 	cfg_tmp = cfg_rcwsrds1 & 0xC;
408 	cfg_tmp >>= 2;
409 	do_serdes_enable(cfg_tmp, serdes2_base);
410 #endif
411 
412 	/* Wait for at at least 625us, ensure the PLLs being reset are locked */
413 	udelay(800);
414 
415 #ifdef CONFIG_SYS_FSL_SRDS_1
416 	cfg_tmp = cfg_rcwsrds1 & 0x3;
417 	do_pll_lock(cfg_tmp, serdes1_base);
418 #endif
419 
420 #ifdef CONFIG_SYS_FSL_SRDS_2
421 	cfg_tmp = cfg_rcwsrds1 & 0xC;
422 	cfg_tmp >>= 2;
423 	do_pll_lock(cfg_tmp, serdes2_base);
424 #endif
425 	/* Take the all enabled lanes out of reset */
426 #ifdef CONFIG_SYS_FSL_SRDS_1
427 	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
428 #endif
429 #ifdef CONFIG_SYS_FSL_SRDS_2
430 	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
431 #endif
432 
433 	/* For each PLL being reset, and achieved PLL lock set RST_DONE */
434 #ifdef CONFIG_SYS_FSL_SRDS_1
435 	cfg_tmp = cfg_rcwsrds1 & 0x3;
436 	do_pll_reset_done(cfg_tmp, serdes1_base);
437 #endif
438 #ifdef CONFIG_SYS_FSL_SRDS_2
439 	cfg_tmp = cfg_rcwsrds1 & 0xC;
440 	cfg_tmp >>= 2;
441 	do_pll_reset_done(cfg_tmp, serdes2_base);
442 #endif
443 
444 	return ret;
445 }
446 
447 void fsl_serdes_init(void)
448 {
449 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
450 	int i , j;
451 
452 	for (i = XFI1, j = 1; i <= XFI8; i++, j++)
453 		xfi_dpmac[i] = j;
454 
455 	for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
456 		sgmii_dpmac[i] = j;
457 #endif
458 
459 #ifdef CONFIG_SYS_FSL_SRDS_1
460 	serdes_init(FSL_SRDS_1,
461 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
462 		    FSL_CHASSIS3_SRDS1_REGSR,
463 		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
464 		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
465 		    serdes1_prtcl_map);
466 #endif
467 #ifdef CONFIG_SYS_FSL_SRDS_2
468 	serdes_init(FSL_SRDS_2,
469 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
470 		    FSL_CHASSIS3_SRDS2_REGSR,
471 		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
472 		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
473 		    serdes2_prtcl_map);
474 #endif
475 }
476