1SoC overview
2
3	1. LS1043A
4	2. LS2080A
5	3. LS1012A
6	4. LS1046A
7	5. LS2088A
8	6. LS2081A
9
10LS1043A
11---------
12The LS1043A integrated multicore processor combines four ARM Cortex-A53
13processor cores with datapath acceleration optimized for L2/3 packet
14processing, single pass security offload and robust traffic management
15and quality of service.
16
17The LS1043A SoC includes the following function and features:
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
21   support
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
23   the following functions:
24   - Packet parsing, classification, and distribution (FMan)
25   - Queue management for scheduling, packet sequencing, and congestion
26     management (QMan)
27   - Hardware buffer management for buffer allocation and de-allocation (BMan)
28   - Cryptography acceleration (SEC)
29 - Ethernet interfaces by FMan
30   - Up to 1 x XFI supporting 10G interface
31   - Up to 1 x QSGMII
32   - Up to 4 x SGMII supporting 1000Mbps
33   - Up to 2 x SGMII supporting 2500Mbps
34   - Up to 2 x RGMII supporting 1000Mbps
35 - High-speed peripheral interfaces
36   - Three PCIe 2.0 controllers, one supporting x4 operation
37   - One serial ATA (SATA 3.0) controllers
38 - Additional peripheral interfaces
39   - Three high-speed USB 3.0 controllers with integrated PHY
40   - Enhanced secure digital host controller (eSDXC/eMMC)
41   - Quad Serial Peripheral Interface (QSPI) Controller
42   - Serial peripheral interface (SPI) controller
43   - Four I2C controllers
44   - Two DUARTs
45   - Integrated flash controller supporting NAND and NOR flash
46 - QorIQ platform's trust architecture 2.1
47
48LS2080A
49--------
50The LS2080A integrated multicore processor combines eight ARM Cortex-A57
51processor cores with high-performance data path acceleration logic and network
52and peripheral bus interfaces required for networking, telecom/datacom,
53wireless infrastructure, and mil/aerospace applications.
54
55The LS2080A SoC includes the following function and features:
56
57 - Eight 64-bit ARM Cortex-A57 CPUs
58 - 1 MB platform cache with ECC
59 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
60 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
61  the AIOP
62 - Data path acceleration architecture (DPAA2) incorporating acceleration for
63 the following functions:
64   - Packet parsing, classification, and distribution (WRIOP)
65   - Queue and Hardware buffer management for scheduling, packet sequencing, and
66     congestion management, buffer allocation and de-allocation (QBMan)
67   - Cryptography acceleration (SEC) at up to 10 Gbps
68   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
69   - Decompression/compression acceleration (DCE) at up to 20 Gbps
70   - Accelerated I/O processing (AIOP) at up to 20 Gbps
71   - QDMA engine
72 - 16 SerDes lanes at up to 10.3125 GHz
73 - Ethernet interfaces
74   - Up to eight 10 Gbps Ethernet MACs
75   - Up to eight 1 / 2.5 Gbps Ethernet MACs
76 - High-speed peripheral interfaces
77   - Four PCIe 3.0 controllers, one supporting SR-IOV
78 - Additional peripheral interfaces
79   - Two serial ATA (SATA 3.0) controllers
80   - Two high-speed USB 3.0 controllers with integrated PHY
81   - Enhanced secure digital host controller (eSDXC/eMMC)
82   - Serial peripheral interface (SPI) controller
83   - Quad Serial Peripheral Interface (QSPI) Controller
84   - Four I2C controllers
85   - Two DUARTs
86   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
87 - Support for hardware virtualization and partitioning enforcement
88 - QorIQ platform's trust architecture 3.0
89 - Service processor (SP) provides pre-boot initialization and secure-boot
90  capabilities
91
92LS1012A
93--------
94The LS1012A features an advanced 64-bit ARM v8 Cortex-
95A53 processor, with 32 KB of parity protected L1-I cache,
9632 KB of ECC protected L1-D cache, as well as 256 KB of
97ECC protected L2 cache.
98
99The LS1012A SoC includes the following function and features:
100 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
101 - ARM v8 cryptography extensions
102 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
103    16-/8-bit operation (no ECC support)
104 - ARM core-link CCI-400 cache coherent interconnect
105 - Packet Forwarding Engine (PFE)
106 - Cryptography acceleration (SEC)
107 - Ethernet interfaces supported by PFE:
108 - One Configurable x3 SerDes:
109    Two Serdes PLLs supported for usage by any SerDes data lane
110    Support for up to 6 GBaud operation
111 - High-speed peripheral interfaces:
112     - One PCI Express Gen2 controller, supporting x1 operation
113     - One serial ATA (SATA Gen 3.0) controller
114     - One USB 3.0/2.0 controller with integrated PHY
115     - One USB 2.0 controller with ULPI interface. .
116 - Additional peripheral interfaces:
117    - One quad serial peripheral interface (QuadSPI) controller
118    - One serial peripheral interface (SPI) controller
119    - Two enhanced secure digital host controllers
120    - Two I2C controllers
121    - One 16550 compliant DUART (two UART interfaces)
122    - Two general purpose IOs (GPIO)
123    - Two FlexTimers
124    - Five synchronous audio interfaces (SAI)
125    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
126    - Single-source clocking solution enabling generation of core, platform,
127    DDR, SerDes, and USB clocks from a single external crystal and internal
128    crystaloscillator
129    - Thermal monitor unit (TMU) with +/- 3C accuracy
130    - Two WatchDog timers
131    - ARM generic timer
132 - QorIQ platform's trust architecture 2.1
133
134LS1046A
135--------
136The LS1046A integrated multicore processor combines four ARM Cortex-A72
137processor cores with datapath acceleration optimized for L2/3 packet
138processing, single pass security offload and robust traffic management
139and quality of service.
140
141The LS1046A SoC includes the following function and features:
142 - Four 64-bit ARM Cortex-A72 CPUs
143 - 2 MB unified L2 Cache
144 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
145   support
146 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
147   the following functions:
148   - Packet parsing, classification, and distribution (FMan)
149   - Queue management for scheduling, packet sequencing, and congestion
150     management (QMan)
151   - Hardware buffer management for buffer allocation and de-allocation (BMan)
152   - Cryptography acceleration (SEC)
153 - Two Configurable x4 SerDes
154   - Two PLLs per four-lane SerDes
155   - Support for 10G operation
156 - Ethernet interfaces by FMan
157   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
158   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
159   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
160   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
161   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
162 - High-speed peripheral interfaces
163   - Three PCIe 3.0 controllers, one supporting x4 operation
164   - One serial ATA (SATA 3.0) controllers
165 - Additional peripheral interfaces
166   - Three high-speed USB 3.0 controllers with integrated PHY
167   - Enhanced secure digital host controller (eSDXC/eMMC)
168   - Quad Serial Peripheral Interface (QSPI) Controller
169   - Serial peripheral interface (SPI) controller
170   - Four I2C controllers
171   - Two DUARTs
172   - Integrated flash controller (IFC) supporting NAND and NOR flash
173 - QorIQ platform's trust architecture 2.1
174
175LS2088A
176--------
177The LS2088A integrated multicore processor combines eight ARM Cortex-A72
178processor cores with high-performance data path acceleration logic and network
179and peripheral bus interfaces required for networking, telecom/datacom,
180wireless infrastructure, and mil/aerospace applications.
181
182The LS2088A SoC includes the following function and features:
183
184 - Eight 64-bit ARM Cortex-A72 CPUs
185 - 1 MB platform cache with ECC
186 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
187 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
188   the AIOP
189 - Data path acceleration architecture (DPAA2) incorporating acceleration for
190   the following functions:
191   - Packet parsing, classification, and distribution (WRIOP)
192   - Queue and Hardware buffer management for scheduling, packet sequencing, and
193     congestion management, buffer allocation and de-allocation (QBMan)
194   - Cryptography acceleration (SEC) at up to 10 Gbps
195   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
196   - Decompression/compression acceleration (DCE) at up to 20 Gbps
197   - Accelerated I/O processing (AIOP) at up to 20 Gbps
198   - QDMA engine
199 - 16 SerDes lanes at up to 10.3125 GHz
200 - Ethernet interfaces
201   - Up to eight 10 Gbps Ethernet MACs
202   - Up to eight 1 / 2.5 Gbps Ethernet MACs
203 - High-speed peripheral interfaces
204   - Four PCIe 3.0 controllers, one supporting SR-IOV
205 - Additional peripheral interfaces
206   - Two serial ATA (SATA 3.0) controllers
207   - Two high-speed USB 3.0 controllers with integrated PHY
208   - Enhanced secure digital host controller (eSDXC/eMMC)
209   - Serial peripheral interface (SPI) controller
210   - Quad Serial Peripheral Interface (QSPI) Controller
211   - Four I2C controllers
212   - Two DUARTs
213   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
214 - Support for hardware virtualization and partitioning enforcement
215 - QorIQ platform's trust architecture 3.0
216 - Service processor (SP) provides pre-boot initialization and secure-boot
217 capabilities
218
219LS2088A SoC has 3 more similar SoC personalities
2201)LS2048A, few difference w.r.t. LS2088A:
221       a) Four 64-bit ARM v8 Cortex-A72 CPUs
222
2232)LS2084A, few difference w.r.t. LS2088A:
224       a) No AIOP
225       b) No 32-bit DDR3 SDRAM memory
226       c) 5 * 1/10G + 5 *1G WRIOP
227       d) No L2 switch
228
2293)LS2044A, few difference w.r.t. LS2084A:
230       a) Four 64-bit ARM v8 Cortex-A72 CPUs
231
232LS2081A
233--------
234LS2081A is 40-pin derivative of LS2084A.
235So feature-wise it is same as LS2084A.
236Refer to LS2084A(LS2088A) section above for details.
237
238It has one more similar SoC personality
2391)LS2041A, few difference w.r.t. LS2081A:
240       a) Four 64-bit ARM v8 Cortex-A72 CPUs
241