1SoC overview
2
3	1. LS1043A
4	2. LS2080A
5	3. LS1012A
6	4. LS1046A
7	5. LS2088A
8
9LS1043A
10---------
11The LS1043A integrated multicore processor combines four ARM Cortex-A53
12processor cores with datapath acceleration optimized for L2/3 packet
13processing, single pass security offload and robust traffic management
14and quality of service.
15
16The LS1043A SoC includes the following function and features:
17 - Four 64-bit ARM Cortex-A53 CPUs
18 - 1 MB unified L2 Cache
19 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
20   support
21 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
22   the following functions:
23   - Packet parsing, classification, and distribution (FMan)
24   - Queue management for scheduling, packet sequencing, and congestion
25     management (QMan)
26   - Hardware buffer management for buffer allocation and de-allocation (BMan)
27   - Cryptography acceleration (SEC)
28 - Ethernet interfaces by FMan
29   - Up to 1 x XFI supporting 10G interface
30   - Up to 1 x QSGMII
31   - Up to 4 x SGMII supporting 1000Mbps
32   - Up to 2 x SGMII supporting 2500Mbps
33   - Up to 2 x RGMII supporting 1000Mbps
34 - High-speed peripheral interfaces
35   - Three PCIe 2.0 controllers, one supporting x4 operation
36   - One serial ATA (SATA 3.0) controllers
37 - Additional peripheral interfaces
38   - Three high-speed USB 3.0 controllers with integrated PHY
39   - Enhanced secure digital host controller (eSDXC/eMMC)
40   - Quad Serial Peripheral Interface (QSPI) Controller
41   - Serial peripheral interface (SPI) controller
42   - Four I2C controllers
43   - Two DUARTs
44   - Integrated flash controller supporting NAND and NOR flash
45 - QorIQ platform's trust architecture 2.1
46
47LS2080A
48--------
49The LS2080A integrated multicore processor combines eight ARM Cortex-A57
50processor cores with high-performance data path acceleration logic and network
51and peripheral bus interfaces required for networking, telecom/datacom,
52wireless infrastructure, and mil/aerospace applications.
53
54The LS2080A SoC includes the following function and features:
55
56 - Eight 64-bit ARM Cortex-A57 CPUs
57 - 1 MB platform cache with ECC
58 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
59 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
60  the AIOP
61 - Data path acceleration architecture (DPAA2) incorporating acceleration for
62 the following functions:
63   - Packet parsing, classification, and distribution (WRIOP)
64   - Queue and Hardware buffer management for scheduling, packet sequencing, and
65     congestion management, buffer allocation and de-allocation (QBMan)
66   - Cryptography acceleration (SEC) at up to 10 Gbps
67   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
68   - Decompression/compression acceleration (DCE) at up to 20 Gbps
69   - Accelerated I/O processing (AIOP) at up to 20 Gbps
70   - QDMA engine
71 - 16 SerDes lanes at up to 10.3125 GHz
72 - Ethernet interfaces
73   - Up to eight 10 Gbps Ethernet MACs
74   - Up to eight 1 / 2.5 Gbps Ethernet MACs
75 - High-speed peripheral interfaces
76   - Four PCIe 3.0 controllers, one supporting SR-IOV
77 - Additional peripheral interfaces
78   - Two serial ATA (SATA 3.0) controllers
79   - Two high-speed USB 3.0 controllers with integrated PHY
80   - Enhanced secure digital host controller (eSDXC/eMMC)
81   - Serial peripheral interface (SPI) controller
82   - Quad Serial Peripheral Interface (QSPI) Controller
83   - Four I2C controllers
84   - Two DUARTs
85   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
86 - Support for hardware virtualization and partitioning enforcement
87 - QorIQ platform's trust architecture 3.0
88 - Service processor (SP) provides pre-boot initialization and secure-boot
89  capabilities
90
91LS1012A
92--------
93The LS1012A features an advanced 64-bit ARM v8 Cortex-
94A53 processor, with 32 KB of parity protected L1-I cache,
9532 KB of ECC protected L1-D cache, as well as 256 KB of
96ECC protected L2 cache.
97
98The LS1012A SoC includes the following function and features:
99 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
100 - ARM v8 cryptography extensions
101 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
102    16-/8-bit operation (no ECC support)
103 - ARM core-link CCI-400 cache coherent interconnect
104 - Packet Forwarding Engine (PFE)
105 - Cryptography acceleration (SEC)
106 - Ethernet interfaces supported by PFE:
107 - One Configurable x3 SerDes:
108    Two Serdes PLLs supported for usage by any SerDes data lane
109    Support for up to 6 GBaud operation
110 - High-speed peripheral interfaces:
111     - One PCI Express Gen2 controller, supporting x1 operation
112     - One serial ATA (SATA Gen 3.0) controller
113     - One USB 3.0/2.0 controller with integrated PHY
114     - One USB 2.0 controller with ULPI interface. .
115 - Additional peripheral interfaces:
116    - One quad serial peripheral interface (QuadSPI) controller
117    - One serial peripheral interface (SPI) controller
118    - Two enhanced secure digital host controllers
119    - Two I2C controllers
120    - One 16550 compliant DUART (two UART interfaces)
121    - Two general purpose IOs (GPIO)
122    - Two FlexTimers
123    - Five synchronous audio interfaces (SAI)
124    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
125    - Single-source clocking solution enabling generation of core, platform,
126    DDR, SerDes, and USB clocks from a single external crystal and internal
127    crystaloscillator
128    - Thermal monitor unit (TMU) with +/- 3C accuracy
129    - Two WatchDog timers
130    - ARM generic timer
131 - QorIQ platform's trust architecture 2.1
132
133LS1046A
134--------
135The LS1046A integrated multicore processor combines four ARM Cortex-A72
136processor cores with datapath acceleration optimized for L2/3 packet
137processing, single pass security offload and robust traffic management
138and quality of service.
139
140The LS1046A SoC includes the following function and features:
141 - Four 64-bit ARM Cortex-A72 CPUs
142 - 2 MB unified L2 Cache
143 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
144   support
145 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
146   the following functions:
147   - Packet parsing, classification, and distribution (FMan)
148   - Queue management for scheduling, packet sequencing, and congestion
149     management (QMan)
150   - Hardware buffer management for buffer allocation and de-allocation (BMan)
151   - Cryptography acceleration (SEC)
152 - Two Configurable x4 SerDes
153   - Two PLLs per four-lane SerDes
154   - Support for 10G operation
155 - Ethernet interfaces by FMan
156   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
157   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
158   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
159   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
160   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
161 - High-speed peripheral interfaces
162   - Three PCIe 3.0 controllers, one supporting x4 operation
163   - One serial ATA (SATA 3.0) controllers
164 - Additional peripheral interfaces
165   - Three high-speed USB 3.0 controllers with integrated PHY
166   - Enhanced secure digital host controller (eSDXC/eMMC)
167   - Quad Serial Peripheral Interface (QSPI) Controller
168   - Serial peripheral interface (SPI) controller
169   - Four I2C controllers
170   - Two DUARTs
171   - Integrated flash controller (IFC) supporting NAND and NOR flash
172 - QorIQ platform's trust architecture 2.1
173
174LS2088A
175--------
176The LS2088A integrated multicore processor combines eight ARM Cortex-A72
177processor cores with high-performance data path acceleration logic and network
178and peripheral bus interfaces required for networking, telecom/datacom,
179wireless infrastructure, and mil/aerospace applications.
180
181The LS2088A SoC includes the following function and features:
182
183 - Eight 64-bit ARM Cortex-A72 CPUs
184 - 1 MB platform cache with ECC
185 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
186 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
187   the AIOP
188 - Data path acceleration architecture (DPAA2) incorporating acceleration for
189   the following functions:
190   - Packet parsing, classification, and distribution (WRIOP)
191   - Queue and Hardware buffer management for scheduling, packet sequencing, and
192     congestion management, buffer allocation and de-allocation (QBMan)
193   - Cryptography acceleration (SEC) at up to 10 Gbps
194   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
195   - Decompression/compression acceleration (DCE) at up to 20 Gbps
196   - Accelerated I/O processing (AIOP) at up to 20 Gbps
197   - QDMA engine
198 - 16 SerDes lanes at up to 10.3125 GHz
199 - Ethernet interfaces
200   - Up to eight 10 Gbps Ethernet MACs
201   - Up to eight 1 / 2.5 Gbps Ethernet MACs
202 - High-speed peripheral interfaces
203   - Four PCIe 3.0 controllers, one supporting SR-IOV
204 - Additional peripheral interfaces
205   - Two serial ATA (SATA 3.0) controllers
206   - Two high-speed USB 3.0 controllers with integrated PHY
207   - Enhanced secure digital host controller (eSDXC/eMMC)
208   - Serial peripheral interface (SPI) controller
209   - Quad Serial Peripheral Interface (QSPI) Controller
210   - Four I2C controllers
211   - Two DUARTs
212   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
213 - Support for hardware virtualization and partitioning enforcement
214 - QorIQ platform's trust architecture 3.0
215 - Service processor (SP) provides pre-boot initialization and secure-boot
216 capabilities
217
218LS2088A SoC has 3 more similar SoC personalities
2191)LS2048A, few difference w.r.t. LS2088A:
220       a) Four 64-bit ARM v8 Cortex-A72 CPUs
221
2222)LS2084A, few difference w.r.t. LS2088A:
223       a) No AIOP
224       b) No 32-bit DDR3 SDRAM memory
225       c) 5 * 1/10G + 5 *1G WRIOP
226       d) No L2 switch
227
2283)LS2044A, few difference w.r.t. LS2084A:
229       a) Four 64-bit ARM v8 Cortex-A72 CPUs
230