1SoC overview
2
3	1. LS1043A
4	2. LS2080A
5	3. LS1012A
6	4. LS1046A
7
8LS1043A
9---------
10The LS1043A integrated multicore processor combines four ARM Cortex-A53
11processor cores with datapath acceleration optimized for L2/3 packet
12processing, single pass security offload and robust traffic management
13and quality of service.
14
15The LS1043A SoC includes the following function and features:
16 - Four 64-bit ARM Cortex-A53 CPUs
17 - 1 MB unified L2 Cache
18 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
19   support
20 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
21   the following functions:
22   - Packet parsing, classification, and distribution (FMan)
23   - Queue management for scheduling, packet sequencing, and congestion
24     management (QMan)
25   - Hardware buffer management for buffer allocation and de-allocation (BMan)
26   - Cryptography acceleration (SEC)
27 - Ethernet interfaces by FMan
28   - Up to 1 x XFI supporting 10G interface
29   - Up to 1 x QSGMII
30   - Up to 4 x SGMII supporting 1000Mbps
31   - Up to 2 x SGMII supporting 2500Mbps
32   - Up to 2 x RGMII supporting 1000Mbps
33 - High-speed peripheral interfaces
34   - Three PCIe 2.0 controllers, one supporting x4 operation
35   - One serial ATA (SATA 3.0) controllers
36 - Additional peripheral interfaces
37   - Three high-speed USB 3.0 controllers with integrated PHY
38   - Enhanced secure digital host controller (eSDXC/eMMC)
39   - Quad Serial Peripheral Interface (QSPI) Controller
40   - Serial peripheral interface (SPI) controller
41   - Four I2C controllers
42   - Two DUARTs
43   - Integrated flash controller supporting NAND and NOR flash
44 - QorIQ platform's trust architecture 2.1
45
46LS2080A
47--------
48The LS2080A integrated multicore processor combines eight ARM Cortex-A57
49processor cores with high-performance data path acceleration logic and network
50and peripheral bus interfaces required for networking, telecom/datacom,
51wireless infrastructure, and mil/aerospace applications.
52
53The LS2080A SoC includes the following function and features:
54
55 - Eight 64-bit ARM Cortex-A57 CPUs
56 - 1 MB platform cache with ECC
57 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
58 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
59  the AIOP
60 - Data path acceleration architecture (DPAA2) incorporating acceleration for
61 the following functions:
62   - Packet parsing, classification, and distribution (WRIOP)
63   - Queue and Hardware buffer management for scheduling, packet sequencing, and
64     congestion management, buffer allocation and de-allocation (QBMan)
65   - Cryptography acceleration (SEC) at up to 10 Gbps
66   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
67   - Decompression/compression acceleration (DCE) at up to 20 Gbps
68   - Accelerated I/O processing (AIOP) at up to 20 Gbps
69   - QDMA engine
70 - 16 SerDes lanes at up to 10.3125 GHz
71 - Ethernet interfaces
72   - Up to eight 10 Gbps Ethernet MACs
73   - Up to eight 1 / 2.5 Gbps Ethernet MACs
74 - High-speed peripheral interfaces
75   - Four PCIe 3.0 controllers, one supporting SR-IOV
76 - Additional peripheral interfaces
77   - Two serial ATA (SATA 3.0) controllers
78   - Two high-speed USB 3.0 controllers with integrated PHY
79   - Enhanced secure digital host controller (eSDXC/eMMC)
80   - Serial peripheral interface (SPI) controller
81   - Quad Serial Peripheral Interface (QSPI) Controller
82   - Four I2C controllers
83   - Two DUARTs
84   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
85 - Support for hardware virtualization and partitioning enforcement
86 - QorIQ platform's trust architecture 3.0
87 - Service processor (SP) provides pre-boot initialization and secure-boot
88  capabilities
89
90LS1012A
91--------
92The LS1012A features an advanced 64-bit ARM v8 Cortex-
93A53 processor, with 32 KB of parity protected L1-I cache,
9432 KB of ECC protected L1-D cache, as well as 256 KB of
95ECC protected L2 cache.
96
97The LS1012A SoC includes the following function and features:
98 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
99 - ARM v8 cryptography extensions
100 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
101    16-/8-bit operation (no ECC support)
102 - ARM core-link CCI-400 cache coherent interconnect
103 - Packet Forwarding Engine (PFE)
104 - Cryptography acceleration (SEC)
105 - Ethernet interfaces supported by PFE:
106 - One Configurable x3 SerDes:
107    Two Serdes PLLs supported for usage by any SerDes data lane
108    Support for up to 6 GBaud operation
109 - High-speed peripheral interfaces:
110     - One PCI Express Gen2 controller, supporting x1 operation
111     - One serial ATA (SATA Gen 3.0) controller
112     - One USB 3.0/2.0 controller with integrated PHY
113     - One USB 2.0 controller with ULPI interface. .
114 - Additional peripheral interfaces:
115    - One quad serial peripheral interface (QuadSPI) controller
116    - One serial peripheral interface (SPI) controller
117    - Two enhanced secure digital host controllers
118    - Two I2C controllers
119    - One 16550 compliant DUART (two UART interfaces)
120    - Two general purpose IOs (GPIO)
121    - Two FlexTimers
122    - Five synchronous audio interfaces (SAI)
123    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
124    - Single-source clocking solution enabling generation of core, platform,
125    DDR, SerDes, and USB clocks from a single external crystal and internal
126    crystaloscillator
127    - Thermal monitor unit (TMU) with +/- 3C accuracy
128    - Two WatchDog timers
129    - ARM generic timer
130 - QorIQ platform's trust architecture 2.1
131
132LS1046A
133--------
134The LS1046A integrated multicore processor combines four ARM Cortex-A72
135processor cores with datapath acceleration optimized for L2/3 packet
136processing, single pass security offload and robust traffic management
137and quality of service.
138
139The LS1046A SoC includes the following function and features:
140 - Four 64-bit ARM Cortex-A72 CPUs
141 - 2 MB unified L2 Cache
142 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
143   support
144 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
145   the following functions:
146   - Packet parsing, classification, and distribution (FMan)
147   - Queue management for scheduling, packet sequencing, and congestion
148     management (QMan)
149   - Hardware buffer management for buffer allocation and de-allocation (BMan)
150   - Cryptography acceleration (SEC)
151 - Two Configurable x4 SerDes
152   - Two PLLs per four-lane SerDes
153   - Support for 10G operation
154 - Ethernet interfaces by FMan
155   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
156   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
157   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
158   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
159   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
160 - High-speed peripheral interfaces
161   - Three PCIe 3.0 controllers, one supporting x4 operation
162   - One serial ATA (SATA 3.0) controllers
163 - Additional peripheral interfaces
164   - Three high-speed USB 3.0 controllers with integrated PHY
165   - Enhanced secure digital host controller (eSDXC/eMMC)
166   - Quad Serial Peripheral Interface (QSPI) Controller
167   - Serial peripheral interface (SPI) controller
168   - Four I2C controllers
169   - Two DUARTs
170   - Integrated flash controller (IFC) supporting NAND and NOR flash
171 - QorIQ platform's trust architecture 2.1
172