1SoC overview
2
3	1. LS1043A
4	2. LS2080A
5	3. LS1012A
6
7LS1043A
8---------
9The LS1043A integrated multicore processor combines four ARM Cortex-A53
10processor cores with datapath acceleration optimized for L2/3 packet
11processing, single pass security offload and robust traffic management
12and quality of service.
13
14The LS1043A SoC includes the following function and features:
15 - Four 64-bit ARM Cortex-A53 CPUs
16 - 1 MB unified L2 Cache
17 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
18   support
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
20   the following functions:
21   - Packet parsing, classification, and distribution (FMan)
22   - Queue management for scheduling, packet sequencing, and congestion
23     management (QMan)
24   - Hardware buffer management for buffer allocation and de-allocation (BMan)
25   - Cryptography acceleration (SEC)
26 - Ethernet interfaces by FMan
27   - Up to 1 x XFI supporting 10G interface
28   - Up to 1 x QSGMII
29   - Up to 4 x SGMII supporting 1000Mbps
30   - Up to 2 x SGMII supporting 2500Mbps
31   - Up to 2 x RGMII supporting 1000Mbps
32 - High-speed peripheral interfaces
33   - Three PCIe 2.0 controllers, one supporting x4 operation
34   - One serial ATA (SATA 3.0) controllers
35 - Additional peripheral interfaces
36   - Three high-speed USB 3.0 controllers with integrated PHY
37   - Enhanced secure digital host controller (eSDXC/eMMC)
38   - Quad Serial Peripheral Interface (QSPI) Controller
39   - Serial peripheral interface (SPI) controller
40   - Four I2C controllers
41   - Two DUARTs
42   - Integrated flash controller supporting NAND and NOR flash
43 - QorIQ platform's trust architecture 2.1
44
45LS2080A
46--------
47The LS2080A integrated multicore processor combines eight ARM Cortex-A57
48processor cores with high-performance data path acceleration logic and network
49and peripheral bus interfaces required for networking, telecom/datacom,
50wireless infrastructure, and mil/aerospace applications.
51
52The LS2080A SoC includes the following function and features:
53
54 - Eight 64-bit ARM Cortex-A57 CPUs
55 - 1 MB platform cache with ECC
56 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
57 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
58  the AIOP
59 - Data path acceleration architecture (DPAA2) incorporating acceleration for
60 the following functions:
61   - Packet parsing, classification, and distribution (WRIOP)
62   - Queue and Hardware buffer management for scheduling, packet sequencing, and
63     congestion management, buffer allocation and de-allocation (QBMan)
64   - Cryptography acceleration (SEC) at up to 10 Gbps
65   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
66   - Decompression/compression acceleration (DCE) at up to 20 Gbps
67   - Accelerated I/O processing (AIOP) at up to 20 Gbps
68   - QDMA engine
69 - 16 SerDes lanes at up to 10.3125 GHz
70 - Ethernet interfaces
71   - Up to eight 10 Gbps Ethernet MACs
72   - Up to eight 1 / 2.5 Gbps Ethernet MACs
73 - High-speed peripheral interfaces
74   - Four PCIe 3.0 controllers, one supporting SR-IOV
75 - Additional peripheral interfaces
76   - Two serial ATA (SATA 3.0) controllers
77   - Two high-speed USB 3.0 controllers with integrated PHY
78   - Enhanced secure digital host controller (eSDXC/eMMC)
79   - Serial peripheral interface (SPI) controller
80   - Quad Serial Peripheral Interface (QSPI) Controller
81   - Four I2C controllers
82   - Two DUARTs
83   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
84 - Support for hardware virtualization and partitioning enforcement
85 - QorIQ platform's trust architecture 3.0
86 - Service processor (SP) provides pre-boot initialization and secure-boot
87  capabilities
88
89LS1012A
90--------
91The LS1012A features an advanced 64-bit ARM v8 Cortex-
92A53 processor, with 32 KB of parity protected L1-I cache,
9332 KB of ECC protected L1-D cache, as well as 256 KB of
94ECC protected L2 cache.
95
96The LS1012A SoC includes the following function and features:
97 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
98 - ARM v8 cryptography extensions
99 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
100    16-/8-bit operation (no ECC support)
101 - ARM core-link CCI-400 cache coherent interconnect
102 - Packet Forwarding Engine (PFE)
103 - Cryptography acceleration (SEC)
104 - Ethernet interfaces supported by PFE:
105 - One Configurable x3 SerDes:
106    Two Serdes PLLs supported for usage by any SerDes data lane
107    Support for up to 6 GBaud operation
108 - High-speed peripheral interfaces:
109     - One PCI Express Gen2 controller, supporting x1 operation
110     - One serial ATA (SATA Gen 3.0) controller
111     - One USB 3.0/2.0 controller with integrated PHY
112     - One USB 2.0 controller with ULPI interface. .
113 - Additional peripheral interfaces:
114    - One quad serial peripheral interface (QuadSPI) controller
115    - One serial peripheral interface (SPI) controller
116    - Two enhanced secure digital host controllers
117    - Two I2C controllers
118    - One 16550 compliant DUART (two UART interfaces)
119    - Two general purpose IOs (GPIO)
120    - Two FlexTimers
121    - Five synchronous audio interfaces (SAI)
122    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
123    - Single-source clocking solution enabling generation of core, platform,
124    DDR, SerDes, and USB clocks from a single external crystal and internal
125    crystaloscillator
126    - Thermal monitor unit (TMU) with +/- 3C accuracy
127    - Two WatchDog timers
128    - ARM generic timer
129 - QorIQ platform's trust architecture 2.1
130