1ddd8a080SPrabhakar KushwahaSoC overview 2ddd8a080SPrabhakar Kushwaha 3ddd8a080SPrabhakar Kushwaha 1. LS1043A 46d9b82d0SAshish Kumar 2. LS1088A 56d9b82d0SAshish Kumar 3. LS2080A 66d9b82d0SAshish Kumar 4. LS1012A 76d9b82d0SAshish Kumar 5. LS1046A 86d9b82d0SAshish Kumar 6. LS2088A 96d9b82d0SAshish Kumar 7. LS2081A 10*4909b89eSPriyanka Jain 8. LX2160A 11ddd8a080SPrabhakar Kushwaha 12ddd8a080SPrabhakar KushwahaLS1043A 13ddd8a080SPrabhakar Kushwaha--------- 14ddd8a080SPrabhakar KushwahaThe LS1043A integrated multicore processor combines four ARM Cortex-A53 15ddd8a080SPrabhakar Kushwahaprocessor cores with datapath acceleration optimized for L2/3 packet 16ddd8a080SPrabhakar Kushwahaprocessing, single pass security offload and robust traffic management 17ddd8a080SPrabhakar Kushwahaand quality of service. 18ddd8a080SPrabhakar Kushwaha 19ddd8a080SPrabhakar KushwahaThe LS1043A SoC includes the following function and features: 20ddd8a080SPrabhakar Kushwaha - Four 64-bit ARM Cortex-A53 CPUs 21ddd8a080SPrabhakar Kushwaha - 1 MB unified L2 Cache 22ddd8a080SPrabhakar Kushwaha - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving 23ddd8a080SPrabhakar Kushwaha support 24ddd8a080SPrabhakar Kushwaha - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 25ddd8a080SPrabhakar Kushwaha the following functions: 26ddd8a080SPrabhakar Kushwaha - Packet parsing, classification, and distribution (FMan) 27ddd8a080SPrabhakar Kushwaha - Queue management for scheduling, packet sequencing, and congestion 28ddd8a080SPrabhakar Kushwaha management (QMan) 29ddd8a080SPrabhakar Kushwaha - Hardware buffer management for buffer allocation and de-allocation (BMan) 30ddd8a080SPrabhakar Kushwaha - Cryptography acceleration (SEC) 31ddd8a080SPrabhakar Kushwaha - Ethernet interfaces by FMan 32ddd8a080SPrabhakar Kushwaha - Up to 1 x XFI supporting 10G interface 33ddd8a080SPrabhakar Kushwaha - Up to 1 x QSGMII 34ddd8a080SPrabhakar Kushwaha - Up to 4 x SGMII supporting 1000Mbps 35ddd8a080SPrabhakar Kushwaha - Up to 2 x SGMII supporting 2500Mbps 36ddd8a080SPrabhakar Kushwaha - Up to 2 x RGMII supporting 1000Mbps 37ddd8a080SPrabhakar Kushwaha - High-speed peripheral interfaces 38ddd8a080SPrabhakar Kushwaha - Three PCIe 2.0 controllers, one supporting x4 operation 39ddd8a080SPrabhakar Kushwaha - One serial ATA (SATA 3.0) controllers 40ddd8a080SPrabhakar Kushwaha - Additional peripheral interfaces 41ddd8a080SPrabhakar Kushwaha - Three high-speed USB 3.0 controllers with integrated PHY 42ddd8a080SPrabhakar Kushwaha - Enhanced secure digital host controller (eSDXC/eMMC) 43ddd8a080SPrabhakar Kushwaha - Quad Serial Peripheral Interface (QSPI) Controller 44ddd8a080SPrabhakar Kushwaha - Serial peripheral interface (SPI) controller 45ddd8a080SPrabhakar Kushwaha - Four I2C controllers 46ddd8a080SPrabhakar Kushwaha - Two DUARTs 47ddd8a080SPrabhakar Kushwaha - Integrated flash controller supporting NAND and NOR flash 48ddd8a080SPrabhakar Kushwaha - QorIQ platform's trust architecture 2.1 49ddd8a080SPrabhakar Kushwaha 506d9b82d0SAshish KumarLS1088A 516d9b82d0SAshish Kumar-------- 526d9b82d0SAshish KumarThe QorIQ LS1088A processor is built on the Layerscape 536d9b82d0SAshish Kumararchitecture combining eight ARM A53 processor cores 546d9b82d0SAshish Kumarwith advanced, high-performance datapath acceleration 556d9b82d0SAshish Kumarand networks, peripheral interfaces required for 566d9b82d0SAshish Kumarnetworking, wireless infrastructure, and general-purpose 576d9b82d0SAshish Kumarembedded applications. 586d9b82d0SAshish Kumar 596d9b82d0SAshish KumarLS1088A is compliant with the Layerscape Chassis Generation 3. 606d9b82d0SAshish Kumar 616d9b82d0SAshish KumarFeatures summary: 626d9b82d0SAshish Kumar - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs 636d9b82d0SAshish Kumar - Cores are in 2 cluster of 4-cores each 646d9b82d0SAshish Kumar - 1MB L2 - Cache per cluster 656d9b82d0SAshish Kumar - Cache coherent interconnect (CCI-400) 666d9b82d0SAshish Kumar - 1 64-bit DDR4 SDRAM memory controller with ECC 676d9b82d0SAshish Kumar - Data path acceleration architecture 2.0 (DPAA2) 686d9b82d0SAshish Kumar - 4-Lane 10GHz SerDes comprising of WRIOP 696d9b82d0SAshish Kumar - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART) 706d9b82d0SAshish Kumar - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs 716d9b82d0SAshish Kumar - QSPI, SPI, IFC2.0 supporting NAND, NOR flash 726d9b82d0SAshish Kumar - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc 736d9b82d0SAshish Kumar - 2 DUARTs 746d9b82d0SAshish Kumar - 4 I2C, GPIO 756d9b82d0SAshish Kumar - Thermal monitor unit(TMU) 766d9b82d0SAshish Kumar - 4 Flextimers and 1 generic timer 776d9b82d0SAshish Kumar - Support for hardware virtualization and partitioning enforcement 786d9b82d0SAshish Kumar - QorIQ platform's trust architecture 3.0 796d9b82d0SAshish Kumar - Service processor (SP) provides pre-boot initialization and secure-boot 806d9b82d0SAshish Kumar capabilities 816d9b82d0SAshish Kumar 82ddd8a080SPrabhakar KushwahaLS2080A 83ddd8a080SPrabhakar Kushwaha-------- 84ddd8a080SPrabhakar KushwahaThe LS2080A integrated multicore processor combines eight ARM Cortex-A57 85ddd8a080SPrabhakar Kushwahaprocessor cores with high-performance data path acceleration logic and network 86ddd8a080SPrabhakar Kushwahaand peripheral bus interfaces required for networking, telecom/datacom, 87ddd8a080SPrabhakar Kushwahawireless infrastructure, and mil/aerospace applications. 88ddd8a080SPrabhakar Kushwaha 89ddd8a080SPrabhakar KushwahaThe LS2080A SoC includes the following function and features: 90ddd8a080SPrabhakar Kushwaha 91ddd8a080SPrabhakar Kushwaha - Eight 64-bit ARM Cortex-A57 CPUs 92ddd8a080SPrabhakar Kushwaha - 1 MB platform cache with ECC 93ddd8a080SPrabhakar Kushwaha - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 94ddd8a080SPrabhakar Kushwaha - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 95ddd8a080SPrabhakar Kushwaha the AIOP 96ddd8a080SPrabhakar Kushwaha - Data path acceleration architecture (DPAA2) incorporating acceleration for 97ddd8a080SPrabhakar Kushwaha the following functions: 98ddd8a080SPrabhakar Kushwaha - Packet parsing, classification, and distribution (WRIOP) 99ddd8a080SPrabhakar Kushwaha - Queue and Hardware buffer management for scheduling, packet sequencing, and 100ddd8a080SPrabhakar Kushwaha congestion management, buffer allocation and de-allocation (QBMan) 101ddd8a080SPrabhakar Kushwaha - Cryptography acceleration (SEC) at up to 10 Gbps 102ddd8a080SPrabhakar Kushwaha - RegEx pattern matching acceleration (PME) at up to 10 Gbps 103ddd8a080SPrabhakar Kushwaha - Decompression/compression acceleration (DCE) at up to 20 Gbps 104ddd8a080SPrabhakar Kushwaha - Accelerated I/O processing (AIOP) at up to 20 Gbps 105ddd8a080SPrabhakar Kushwaha - QDMA engine 106ddd8a080SPrabhakar Kushwaha - 16 SerDes lanes at up to 10.3125 GHz 107ddd8a080SPrabhakar Kushwaha - Ethernet interfaces 108ddd8a080SPrabhakar Kushwaha - Up to eight 10 Gbps Ethernet MACs 109ddd8a080SPrabhakar Kushwaha - Up to eight 1 / 2.5 Gbps Ethernet MACs 110ddd8a080SPrabhakar Kushwaha - High-speed peripheral interfaces 111ddd8a080SPrabhakar Kushwaha - Four PCIe 3.0 controllers, one supporting SR-IOV 112ddd8a080SPrabhakar Kushwaha - Additional peripheral interfaces 113ddd8a080SPrabhakar Kushwaha - Two serial ATA (SATA 3.0) controllers 114ddd8a080SPrabhakar Kushwaha - Two high-speed USB 3.0 controllers with integrated PHY 115ddd8a080SPrabhakar Kushwaha - Enhanced secure digital host controller (eSDXC/eMMC) 116ddd8a080SPrabhakar Kushwaha - Serial peripheral interface (SPI) controller 117ddd8a080SPrabhakar Kushwaha - Quad Serial Peripheral Interface (QSPI) Controller 118ddd8a080SPrabhakar Kushwaha - Four I2C controllers 119ddd8a080SPrabhakar Kushwaha - Two DUARTs 120ddd8a080SPrabhakar Kushwaha - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 121ddd8a080SPrabhakar Kushwaha - Support for hardware virtualization and partitioning enforcement 122ddd8a080SPrabhakar Kushwaha - QorIQ platform's trust architecture 3.0 123ddd8a080SPrabhakar Kushwaha - Service processor (SP) provides pre-boot initialization and secure-boot 124ddd8a080SPrabhakar Kushwaha capabilities 125b7f2bbffSPrabhakar Kushwaha 126b7f2bbffSPrabhakar KushwahaLS1012A 127b7f2bbffSPrabhakar Kushwaha-------- 128b7f2bbffSPrabhakar KushwahaThe LS1012A features an advanced 64-bit ARM v8 Cortex- 129b7f2bbffSPrabhakar KushwahaA53 processor, with 32 KB of parity protected L1-I cache, 130b7f2bbffSPrabhakar Kushwaha32 KB of ECC protected L1-D cache, as well as 256 KB of 131b7f2bbffSPrabhakar KushwahaECC protected L2 cache. 132b7f2bbffSPrabhakar Kushwaha 133b7f2bbffSPrabhakar KushwahaThe LS1012A SoC includes the following function and features: 134b7f2bbffSPrabhakar Kushwaha - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: 135b7f2bbffSPrabhakar Kushwaha - ARM v8 cryptography extensions 136b7f2bbffSPrabhakar Kushwaha - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports 137b7f2bbffSPrabhakar Kushwaha 16-/8-bit operation (no ECC support) 138b7f2bbffSPrabhakar Kushwaha - ARM core-link CCI-400 cache coherent interconnect 139b7f2bbffSPrabhakar Kushwaha - Packet Forwarding Engine (PFE) 140b7f2bbffSPrabhakar Kushwaha - Cryptography acceleration (SEC) 141b7f2bbffSPrabhakar Kushwaha - Ethernet interfaces supported by PFE: 142b7f2bbffSPrabhakar Kushwaha - One Configurable x3 SerDes: 143b7f2bbffSPrabhakar Kushwaha Two Serdes PLLs supported for usage by any SerDes data lane 144b7f2bbffSPrabhakar Kushwaha Support for up to 6 GBaud operation 145b7f2bbffSPrabhakar Kushwaha - High-speed peripheral interfaces: 146b7f2bbffSPrabhakar Kushwaha - One PCI Express Gen2 controller, supporting x1 operation 147b7f2bbffSPrabhakar Kushwaha - One serial ATA (SATA Gen 3.0) controller 148b7f2bbffSPrabhakar Kushwaha - One USB 3.0/2.0 controller with integrated PHY 149b7f2bbffSPrabhakar Kushwaha - One USB 2.0 controller with ULPI interface. . 150b7f2bbffSPrabhakar Kushwaha - Additional peripheral interfaces: 151b7f2bbffSPrabhakar Kushwaha - One quad serial peripheral interface (QuadSPI) controller 152b7f2bbffSPrabhakar Kushwaha - One serial peripheral interface (SPI) controller 153b7f2bbffSPrabhakar Kushwaha - Two enhanced secure digital host controllers 154b7f2bbffSPrabhakar Kushwaha - Two I2C controllers 155b7f2bbffSPrabhakar Kushwaha - One 16550 compliant DUART (two UART interfaces) 156b7f2bbffSPrabhakar Kushwaha - Two general purpose IOs (GPIO) 157b7f2bbffSPrabhakar Kushwaha - Two FlexTimers 158b7f2bbffSPrabhakar Kushwaha - Five synchronous audio interfaces (SAI) 159b7f2bbffSPrabhakar Kushwaha - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading 160b7f2bbffSPrabhakar Kushwaha - Single-source clocking solution enabling generation of core, platform, 161b7f2bbffSPrabhakar Kushwaha DDR, SerDes, and USB clocks from a single external crystal and internal 162b7f2bbffSPrabhakar Kushwaha crystaloscillator 163b7f2bbffSPrabhakar Kushwaha - Thermal monitor unit (TMU) with +/- 3C accuracy 164b7f2bbffSPrabhakar Kushwaha - Two WatchDog timers 165b7f2bbffSPrabhakar Kushwaha - ARM generic timer 166b7f2bbffSPrabhakar Kushwaha - QorIQ platform's trust architecture 2.1 167b528b937SMingkai Hu 168b528b937SMingkai HuLS1046A 169b528b937SMingkai Hu-------- 170b528b937SMingkai HuThe LS1046A integrated multicore processor combines four ARM Cortex-A72 171b528b937SMingkai Huprocessor cores with datapath acceleration optimized for L2/3 packet 172b528b937SMingkai Huprocessing, single pass security offload and robust traffic management 173b528b937SMingkai Huand quality of service. 174b528b937SMingkai Hu 175b528b937SMingkai HuThe LS1046A SoC includes the following function and features: 176b528b937SMingkai Hu - Four 64-bit ARM Cortex-A72 CPUs 177b528b937SMingkai Hu - 2 MB unified L2 Cache 178b528b937SMingkai Hu - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving 179b528b937SMingkai Hu support 180b528b937SMingkai Hu - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 181b528b937SMingkai Hu the following functions: 182b528b937SMingkai Hu - Packet parsing, classification, and distribution (FMan) 183b528b937SMingkai Hu - Queue management for scheduling, packet sequencing, and congestion 184b528b937SMingkai Hu management (QMan) 185b528b937SMingkai Hu - Hardware buffer management for buffer allocation and de-allocation (BMan) 186b528b937SMingkai Hu - Cryptography acceleration (SEC) 187b528b937SMingkai Hu - Two Configurable x4 SerDes 188b528b937SMingkai Hu - Two PLLs per four-lane SerDes 189b528b937SMingkai Hu - Support for 10G operation 190b528b937SMingkai Hu - Ethernet interfaces by FMan 191b528b937SMingkai Hu - Up to 2 x XFI supporting 10G interface (MAC 9, 10) 192b528b937SMingkai Hu - Up to 1 x QSGMII (MAC 5, 6, 10, 1) 193b528b937SMingkai Hu - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) 194b528b937SMingkai Hu - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) 195b528b937SMingkai Hu - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) 196b528b937SMingkai Hu - High-speed peripheral interfaces 197b528b937SMingkai Hu - Three PCIe 3.0 controllers, one supporting x4 operation 198b528b937SMingkai Hu - One serial ATA (SATA 3.0) controllers 199b528b937SMingkai Hu - Additional peripheral interfaces 200b528b937SMingkai Hu - Three high-speed USB 3.0 controllers with integrated PHY 201b528b937SMingkai Hu - Enhanced secure digital host controller (eSDXC/eMMC) 202b528b937SMingkai Hu - Quad Serial Peripheral Interface (QSPI) Controller 203b528b937SMingkai Hu - Serial peripheral interface (SPI) controller 204b528b937SMingkai Hu - Four I2C controllers 205b528b937SMingkai Hu - Two DUARTs 206b528b937SMingkai Hu - Integrated flash controller (IFC) supporting NAND and NOR flash 207b528b937SMingkai Hu - QorIQ platform's trust architecture 2.1 2089ae836cdSPriyanka Jain 2099ae836cdSPriyanka JainLS2088A 2109ae836cdSPriyanka Jain-------- 2119ae836cdSPriyanka JainThe LS2088A integrated multicore processor combines eight ARM Cortex-A72 2129ae836cdSPriyanka Jainprocessor cores with high-performance data path acceleration logic and network 2139ae836cdSPriyanka Jainand peripheral bus interfaces required for networking, telecom/datacom, 2149ae836cdSPriyanka Jainwireless infrastructure, and mil/aerospace applications. 2159ae836cdSPriyanka Jain 2169ae836cdSPriyanka JainThe LS2088A SoC includes the following function and features: 2179ae836cdSPriyanka Jain 2189ae836cdSPriyanka Jain - Eight 64-bit ARM Cortex-A72 CPUs 2199ae836cdSPriyanka Jain - 1 MB platform cache with ECC 2209ae836cdSPriyanka Jain - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 2219ae836cdSPriyanka Jain - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 2229ae836cdSPriyanka Jain the AIOP 2239ae836cdSPriyanka Jain - Data path acceleration architecture (DPAA2) incorporating acceleration for 2249ae836cdSPriyanka Jain the following functions: 2259ae836cdSPriyanka Jain - Packet parsing, classification, and distribution (WRIOP) 2269ae836cdSPriyanka Jain - Queue and Hardware buffer management for scheduling, packet sequencing, and 2279ae836cdSPriyanka Jain congestion management, buffer allocation and de-allocation (QBMan) 2289ae836cdSPriyanka Jain - Cryptography acceleration (SEC) at up to 10 Gbps 2299ae836cdSPriyanka Jain - RegEx pattern matching acceleration (PME) at up to 10 Gbps 2309ae836cdSPriyanka Jain - Decompression/compression acceleration (DCE) at up to 20 Gbps 2319ae836cdSPriyanka Jain - Accelerated I/O processing (AIOP) at up to 20 Gbps 2329ae836cdSPriyanka Jain - QDMA engine 2339ae836cdSPriyanka Jain - 16 SerDes lanes at up to 10.3125 GHz 2349ae836cdSPriyanka Jain - Ethernet interfaces 2359ae836cdSPriyanka Jain - Up to eight 10 Gbps Ethernet MACs 2369ae836cdSPriyanka Jain - Up to eight 1 / 2.5 Gbps Ethernet MACs 2379ae836cdSPriyanka Jain - High-speed peripheral interfaces 2389ae836cdSPriyanka Jain - Four PCIe 3.0 controllers, one supporting SR-IOV 2399ae836cdSPriyanka Jain - Additional peripheral interfaces 2409ae836cdSPriyanka Jain - Two serial ATA (SATA 3.0) controllers 2419ae836cdSPriyanka Jain - Two high-speed USB 3.0 controllers with integrated PHY 2429ae836cdSPriyanka Jain - Enhanced secure digital host controller (eSDXC/eMMC) 2439ae836cdSPriyanka Jain - Serial peripheral interface (SPI) controller 2449ae836cdSPriyanka Jain - Quad Serial Peripheral Interface (QSPI) Controller 2459ae836cdSPriyanka Jain - Four I2C controllers 2469ae836cdSPriyanka Jain - Two DUARTs 2479ae836cdSPriyanka Jain - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 2489ae836cdSPriyanka Jain - Support for hardware virtualization and partitioning enforcement 2499ae836cdSPriyanka Jain - QorIQ platform's trust architecture 3.0 2509ae836cdSPriyanka Jain - Service processor (SP) provides pre-boot initialization and secure-boot 2519ae836cdSPriyanka Jain capabilities 2529ae836cdSPriyanka Jain 2539ae836cdSPriyanka JainLS2088A SoC has 3 more similar SoC personalities 2549ae836cdSPriyanka Jain1)LS2048A, few difference w.r.t. LS2088A: 2559ae836cdSPriyanka Jain a) Four 64-bit ARM v8 Cortex-A72 CPUs 2569ae836cdSPriyanka Jain 2579ae836cdSPriyanka Jain2)LS2084A, few difference w.r.t. LS2088A: 2589ae836cdSPriyanka Jain a) No AIOP 2599ae836cdSPriyanka Jain b) No 32-bit DDR3 SDRAM memory 2609ae836cdSPriyanka Jain c) 5 * 1/10G + 5 *1G WRIOP 2619ae836cdSPriyanka Jain d) No L2 switch 2629ae836cdSPriyanka Jain 2639ae836cdSPriyanka Jain3)LS2044A, few difference w.r.t. LS2084A: 2649ae836cdSPriyanka Jain a) Four 64-bit ARM v8 Cortex-A72 CPUs 265e809e747SPriyanka Jain 266e809e747SPriyanka JainLS2081A 267e809e747SPriyanka Jain-------- 268e809e747SPriyanka JainLS2081A is 40-pin derivative of LS2084A. 269e809e747SPriyanka JainSo feature-wise it is same as LS2084A. 270e809e747SPriyanka JainRefer to LS2084A(LS2088A) section above for details. 271e809e747SPriyanka Jain 272e809e747SPriyanka JainIt has one more similar SoC personality 273e809e747SPriyanka Jain1)LS2041A, few difference w.r.t. LS2081A: 274e809e747SPriyanka Jain a) Four 64-bit ARM v8 Cortex-A72 CPUs 275*4909b89eSPriyanka Jain 276*4909b89eSPriyanka JainLX2160A 277*4909b89eSPriyanka Jain-------- 278*4909b89eSPriyanka JainThe QorIQ LX2160A processor is built in the 16FFC process on 279*4909b89eSPriyanka Jainthe Layerscape architecture combining sixteen ARM A72 processor 280*4909b89eSPriyanka Jaincores with advanced, high-performance datapath acceleration and 281*4909b89eSPriyanka Jainnetwork, peripheral interfaces required for networking, wireless 282*4909b89eSPriyanka Jaininfrastructure, storage, and general-purpose embedded applications. 283*4909b89eSPriyanka Jain 284*4909b89eSPriyanka JainLX2160A is compliant with the Layerscape Chassis Generation 3.2. 285*4909b89eSPriyanka Jain 286*4909b89eSPriyanka JainThe LX2160A SoC includes the following function and features: 287*4909b89eSPriyanka Jain Sixteen 32-bit / 64-bit ARM v8 A72 CPUs 288*4909b89eSPriyanka Jain Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) 289*4909b89eSPriyanka Jain Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. 290*4909b89eSPriyanka Jain Data path acceleration architecture (DPAA2) 291*4909b89eSPriyanka Jain 24 Serdes lanes at up to 25 GHz 292*4909b89eSPriyanka Jain Ethernet interfaces 293*4909b89eSPriyanka Jain Single WRIOP tile supporting 130Gbps using 18 MACs 294*4909b89eSPriyanka Jain Support for 10G-SXGMII (aka USXGMII). 295*4909b89eSPriyanka Jain Support for SGMII (and 1000Base-KX) 296*4909b89eSPriyanka Jain Support for XFI (and 10GBase-KR) 297*4909b89eSPriyanka Jain Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). 298*4909b89eSPriyanka Jain Support for XLAUI (and 40GBase-KR4) for 40G. 299*4909b89eSPriyanka Jain Support for two RGMII parallel interfaces. 300*4909b89eSPriyanka Jain Energy efficient Ethernet support (802.3az) 301*4909b89eSPriyanka Jain IEEE 1588 support. 302*4909b89eSPriyanka Jain High-speed peripheral interfaces 303*4909b89eSPriyanka Jain Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, 304*4909b89eSPriyanka Jain Four PCIe Gen 4.0 4-lane controllers. 305*4909b89eSPriyanka Jain Four serial ATA (SATA 3.0) controllers. 306*4909b89eSPriyanka Jain Two USB 3.0 controllers with integrated PHY 307*4909b89eSPriyanka Jain Two Enhanced secure digital host controllers 308*4909b89eSPriyanka Jain Two Controller Area Network (CAN) modules 309*4909b89eSPriyanka Jain Flexible Serial peripheral interface (FlexSPI) controller. 310*4909b89eSPriyanka Jain Three Serial peripheral interface (SPI) controllers. 311*4909b89eSPriyanka Jain Eight I2C Controllers. 312*4909b89eSPriyanka Jain Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. 313*4909b89eSPriyanka Jain General Purpose IO (GPIO) 314*4909b89eSPriyanka Jain Support for hardware virtualization and partitioning (ARM MMU-500) 315*4909b89eSPriyanka Jain Support for GIC (ARM GIC-500) 316*4909b89eSPriyanka Jain QorIQ platform Trust Architecture 3.0 317*4909b89eSPriyanka Jain One Secure WatchDog timer and one Non-Secure Watchdog timer. 318*4909b89eSPriyanka Jain ARM Generic Timer 319*4909b89eSPriyanka Jain Two Flextimers 320*4909b89eSPriyanka Jain Debug supporting run control, data acquisition, high-speed trace, 321*4909b89eSPriyanka Jain performance/event monitoring 322*4909b89eSPriyanka Jain Thermal Monitor Unit (TMU) with +/- 2C accuracy 323*4909b89eSPriyanka Jain Support for Voltage ID (VID) for yield improvement 324*4909b89eSPriyanka Jain 325*4909b89eSPriyanka JainLX2160A SoC has 2 more similar SoC personalities 326*4909b89eSPriyanka Jain1)LX2120A, few difference w.r.t. LX2160A: 327*4909b89eSPriyanka Jain a) Twelve 64-bit ARM v8 Cortex-A72 CPUs 328*4909b89eSPriyanka Jain 329*4909b89eSPriyanka Jain2)LX2080A, few difference w.r.t. LX2160A: 330*4909b89eSPriyanka Jain a) Eight 64-bit ARM v8 Cortex-A72 CPUs 331