1#
2# Copyright 2018 NXP
3#
4# SPDX-License-Identifier:      GPL-2.0+
5#
6
7NXP LayerScape with Chassis Generation 3.2
8
9This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
10for example LX2160A.
11
12This architecture is enhancement over Chassis Generation 3 with
13few differences mentioned below
14
151)DDR Layout
16============
17Entire DDR region splits into three regions.
18 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
19 - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
20 - Region 3 is at address 0x60_0000_0000 to the top of memory,
21   for example 140GB, 0x63_7fff_ffff.
22
23All DDR memory is marked as cache-enabled.
24
252)IFC is removed
26
273)Number of I2C controllers increased to 8
28