1ddd8a080SPrabhakar Kushwaha# 2ddd8a080SPrabhakar Kushwaha# Copyright 2014-2015 Freescale Semiconductor 3ddd8a080SPrabhakar Kushwaha# 4ddd8a080SPrabhakar Kushwaha# SPDX-License-Identifier: GPL-2.0+ 5ddd8a080SPrabhakar Kushwaha# 6ddd8a080SPrabhakar Kushwaha 7ddd8a080SPrabhakar KushwahaFreescale LayerScape with Chassis Generation 3 8ddd8a080SPrabhakar Kushwaha 9ddd8a080SPrabhakar KushwahaThis architecture supports Freescale ARMv8 SoCs with Chassis generation 3, 10ddd8a080SPrabhakar Kushwahafor example LS2080A. 11ddd8a080SPrabhakar Kushwaha 12ddd8a080SPrabhakar KushwahaDDR Layout 13ddd8a080SPrabhakar Kushwaha============ 14ddd8a080SPrabhakar KushwahaEntire DDR region splits into two regions. 15ddd8a080SPrabhakar Kushwaha - Region 1 is at address 0x8000_0000 to 0xffff_ffff. 16ddd8a080SPrabhakar Kushwaha - Region 2 is at 0x80_8000_0000 to the top of total memory, 17ddd8a080SPrabhakar Kushwaha for example 16GB, 0x83_ffff_ffff. 18ddd8a080SPrabhakar Kushwaha 19ddd8a080SPrabhakar KushwahaAll DDR memory is marked as cache-enabled. 20ddd8a080SPrabhakar Kushwaha 21ddd8a080SPrabhakar KushwahaWhen MC and Debug server is enabled, they carve 512MB away from the high 22ddd8a080SPrabhakar Kushwahaend of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB 23ddd8a080SPrabhakar Kushwahawith MC and Debug server enabled. Linux only sees 15.5GB. 24ddd8a080SPrabhakar Kushwaha 25ddd8a080SPrabhakar KushwahaThe reserved 512MB layout looks like 26ddd8a080SPrabhakar Kushwaha 27ddd8a080SPrabhakar Kushwaha +---------------+ <-- top/end of memory 28ddd8a080SPrabhakar Kushwaha | 256MB | debug server 29ddd8a080SPrabhakar Kushwaha +---------------+ 30ddd8a080SPrabhakar Kushwaha | 256MB | MC 31ddd8a080SPrabhakar Kushwaha +---------------+ 32ddd8a080SPrabhakar Kushwaha | ... | 33ddd8a080SPrabhakar Kushwaha 34ddd8a080SPrabhakar KushwahaMC requires the memory to be aligned with 512MB, so even debug server is 35ddd8a080SPrabhakar Kushwahanot enabled, 512MB is reserved, not 256MB. 36ddd8a080SPrabhakar Kushwaha 37ddd8a080SPrabhakar KushwahaFlash Layout 38ddd8a080SPrabhakar Kushwaha============ 39ddd8a080SPrabhakar Kushwaha 40ddd8a080SPrabhakar Kushwaha(1) A typical layout of various images (including Linux and other firmware images) 41ddd8a080SPrabhakar Kushwaha is shown below considering a 32MB NOR flash device present on most 42ddd8a080SPrabhakar Kushwaha pre-silicon platforms (simulator and emulator): 43ddd8a080SPrabhakar Kushwaha 44ddd8a080SPrabhakar Kushwaha ------------------------- 45ddd8a080SPrabhakar Kushwaha | FIT Image | 46ddd8a080SPrabhakar Kushwaha | (linux + DTB + RFS) | 47ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0120_0000 48ddd8a080SPrabhakar Kushwaha | Debug Server FW | 49ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x00C0_0000 50ddd8a080SPrabhakar Kushwaha | AIOP FW | 51ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0070_0000 52ddd8a080SPrabhakar Kushwaha | MC FW | 53ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x006C_0000 54ddd8a080SPrabhakar Kushwaha | MC DPL Blob | 55ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0020_0000 56ddd8a080SPrabhakar Kushwaha | BootLoader + Env| 57ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0000_1000 58ddd8a080SPrabhakar Kushwaha | PBI | 59ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0000_0080 60ddd8a080SPrabhakar Kushwaha | RCW | 61ddd8a080SPrabhakar Kushwaha ------------------------- ----> 0x0000_0000 62ddd8a080SPrabhakar Kushwaha 63ddd8a080SPrabhakar Kushwaha 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) 64ddd8a080SPrabhakar Kushwaha 65ddd8a080SPrabhakar Kushwaha(2) A typical layout of various images (including Linux and other firmware images) 66ddd8a080SPrabhakar Kushwaha is shown below considering a 128MB NOR flash device present on QDS and RDB 67ddd8a080SPrabhakar Kushwaha boards: 68ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8800_0000 --- 69ddd8a080SPrabhakar Kushwaha | .. Unused .. (7M) | | 70ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8790_0000 | 71ddd8a080SPrabhakar Kushwaha | FIT Image (linux + DTB + RFS) (40M) | | 72ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8510_0000 | 73ddd8a080SPrabhakar Kushwaha | PHY firmware (2M) | | 74ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_84F0_0000 | 64K 75ddd8a080SPrabhakar Kushwaha | Debug Server FW (2M) | | Alt 76ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_84D0_0000 | Bank 77ddd8a080SPrabhakar Kushwaha | AIOP FW (4M) | | 78ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8490_0000 (vbank4) 79ddd8a080SPrabhakar Kushwaha | MC DPC Blob (1M) | | 80ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8480_0000 | 81ddd8a080SPrabhakar Kushwaha | MC DPL Blob (1M) | | 82ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8470_0000 | 83ddd8a080SPrabhakar Kushwaha | MC FW (4M) | | 84ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8430_0000 | 85ddd8a080SPrabhakar Kushwaha | BootLoader Environment (1M) | | 86ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8420_0000 | 87ddd8a080SPrabhakar Kushwaha | BootLoader (1M) | | 88ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8410_0000 | 89ddd8a080SPrabhakar Kushwaha | RCW and PBI (1M) | | 90ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8400_0000 --- 91ddd8a080SPrabhakar Kushwaha | .. Unused .. (7M) | | 92ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8390_0000 | 93ddd8a080SPrabhakar Kushwaha | FIT Image (linux + DTB + RFS) (40M) | | 94ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8110_0000 | 95ddd8a080SPrabhakar Kushwaha | PHY firmware (2M) | | 96ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_80F0_0000 | 64K 97ddd8a080SPrabhakar Kushwaha | Debug Server FW (2M) | | Bank 98ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_80D0_0000 | 99ddd8a080SPrabhakar Kushwaha | AIOP FW (4M) | | 100ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8090_0000 (vbank0) 101ddd8a080SPrabhakar Kushwaha | MC DPC Blob (1M) | | 102ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8080_0000 | 103ddd8a080SPrabhakar Kushwaha | MC DPL Blob (1M) | | 104ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8070_0000 | 105ddd8a080SPrabhakar Kushwaha | MC FW (4M) | | 106ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8030_0000 | 107ddd8a080SPrabhakar Kushwaha | BootLoader Environment (1M) | | 108ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8020_0000 | 109ddd8a080SPrabhakar Kushwaha | BootLoader (1M) | | 110ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8010_0000 | 111ddd8a080SPrabhakar Kushwaha | RCW and PBI (1M) | | 112ddd8a080SPrabhakar Kushwaha ----------------------------------------- ----> 0x5_8000_0000 --- 113ddd8a080SPrabhakar Kushwaha 114ddd8a080SPrabhakar Kushwaha 128-MB NOR flash layout for QDS and RDB boards 115ddd8a080SPrabhakar Kushwaha 116ddd8a080SPrabhakar KushwahaEnvironment Variables 117ddd8a080SPrabhakar Kushwaha===================== 118ddd8a080SPrabhakar Kushwahamcboottimeout: MC boot timeout in milliseconds. If this variable is not defined 119ddd8a080SPrabhakar Kushwaha the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. 120ddd8a080SPrabhakar Kushwaha 121ddd8a080SPrabhakar Kushwahamcmemsize: MC DRAM block size. If this variable is not defined, the value 122ddd8a080SPrabhakar Kushwaha CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. 123ddd8a080SPrabhakar Kushwaha 124*30677deeSPratiyush Mohan Srivastavamcinitcmd: This environment variable is defined to initiate MC and DPL deployment 125*30677deeSPratiyush Mohan Srivastava from the location where it is stored(NOR, NAND, SD, SATA, USB)during 126*30677deeSPratiyush Mohan Srivastava u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR 127*30677deeSPratiyush Mohan Srivastava will be null and MC will not be booted and DPL will not be applied 128*30677deeSPratiyush Mohan Srivastava during U-boot booting.However the MC, DPC and DPL can be applied from 129*30677deeSPratiyush Mohan Srivastava console independently. 130*30677deeSPratiyush Mohan Srivastava The variable needs to be set from the console once and then on 131*30677deeSPratiyush Mohan Srivastava rebooting the parameters set in the varible will automatically be 132*30677deeSPratiyush Mohan Srivastava executed. The commmand is demostrated taking an example of mc boot 133*30677deeSPratiyush Mohan Srivastava using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash: 134*30677deeSPratiyush Mohan Srivastava 135*30677deeSPratiyush Mohan Srivastava cp.b 0xa0000000 0x580300000 $filesize 136*30677deeSPratiyush Mohan Srivastava cp.b 0x80000000 0x580800000 $filesize 137*30677deeSPratiyush Mohan Srivastava cp.b 0x90000000 0x580700000 $filesize 138*30677deeSPratiyush Mohan Srivastava 139*30677deeSPratiyush Mohan Srivastava setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000' 140*30677deeSPratiyush Mohan Srivastava 141*30677deeSPratiyush Mohan Srivastava If only linux is to be booted then the mcinitcmd environment should be set as 142*30677deeSPratiyush Mohan Srivastava 143*30677deeSPratiyush Mohan Srivastava setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 144*30677deeSPratiyush Mohan Srivastava 145*30677deeSPratiyush Mohan Srivastava Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where 146*30677deeSPratiyush Mohan Srivastava MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000 147*30677deeSPratiyush Mohan Srivastava and 0x580700000 are addresses in NOR where these are copied. It is to be 148*30677deeSPratiyush Mohan Srivastava noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 149*30677deeSPratiyush Mohan Srivastava can be replaced with the addresses of DDR to 150*30677deeSPratiyush Mohan Srivastava which these will be copied in case of these binaries being stored in other 151*30677deeSPratiyush Mohan Srivastava devices like SATA, USB, NAND, SD etc. 152*30677deeSPratiyush Mohan Srivastava 153ddd8a080SPrabhakar KushwahaBooting from NAND 154ddd8a080SPrabhakar Kushwaha------------------- 155ddd8a080SPrabhakar KushwahaBooting from NAND requires two images, RCW and u-boot-with-spl.bin. 156ddd8a080SPrabhakar KushwahaThe difference between NAND boot RCW image and NOR boot image is the PBI 157ddd8a080SPrabhakar Kushwahacommand sequence. Below is one example for PBI commands for QDS which uses 158ddd8a080SPrabhakar KushwahaNAND device with 2KB/page, block size 128KB. 159ddd8a080SPrabhakar Kushwaha 160ddd8a080SPrabhakar Kushwaha1) CCSR 4-byte write to 0x00e00404, data=0x00000000 161ddd8a080SPrabhakar Kushwaha2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 162ddd8a080SPrabhakar KushwahaThe above two commands set bootloc register to 0x00000000_1800a000 where 163ddd8a080SPrabhakar Kushwahathe u-boot code will be running in OCRAM. 164ddd8a080SPrabhakar Kushwaha 165ddd8a080SPrabhakar Kushwaha3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, 166ddd8a080SPrabhakar KushwahaBLOCK_SIZE=0x00014000 167ddd8a080SPrabhakar KushwahaThis command copies u-boot image from NAND device into OCRAM. The values need 168ddd8a080SPrabhakar Kushwahato adjust accordingly. 169ddd8a080SPrabhakar Kushwaha 170ddd8a080SPrabhakar KushwahaSRC should match the cfg_rcw_src, the reset config pins. It depends 171ddd8a080SPrabhakar Kushwaha on the NAND device. See reference manual for cfg_rcw_src. 172ddd8a080SPrabhakar KushwahaSRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In 173ddd8a080SPrabhakar Kushwaha the example above, 128KB. For easy maintenance, we put it at 174ddd8a080SPrabhakar Kushwaha the beginning of next block from RCW. 175ddd8a080SPrabhakar KushwahaDEST_ADDR is fixed at 0x1800a000, matching bootloc set above. 176ddd8a080SPrabhakar KushwahaBLOCK_SIZE is the size to be copied by PBI. 177ddd8a080SPrabhakar Kushwaha 178ddd8a080SPrabhakar KushwahaRCW image should be written to the beginning of NAND device. Example of using 179ddd8a080SPrabhakar Kushwahau-boot command 180ddd8a080SPrabhakar Kushwaha 181ddd8a080SPrabhakar Kushwahanand write <rcw image in memory> 0 <size of rcw image> 182ddd8a080SPrabhakar Kushwaha 183ddd8a080SPrabhakar KushwahaTo form the NAND image, build u-boot with NAND config, for example, 184ddd8a080SPrabhakar Kushwahals2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. 185ddd8a080SPrabhakar KushwahaThe u-boot image should be written to match SRC_ADDR, in above example 0x20000. 186ddd8a080SPrabhakar Kushwaha 187ddd8a080SPrabhakar Kushwahanand write <u-boot image in memory> 200000 <size of u-boot image> 188ddd8a080SPrabhakar Kushwaha 189ddd8a080SPrabhakar KushwahaWith these two images in NAND device, the board can boot from NAND. 190ddd8a080SPrabhakar Kushwaha 191ddd8a080SPrabhakar KushwahaAnother example for RDB boards, 192ddd8a080SPrabhakar Kushwaha 193ddd8a080SPrabhakar Kushwaha1) CCSR 4-byte write to 0x00e00404, data=0x00000000 194ddd8a080SPrabhakar Kushwaha2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 195ddd8a080SPrabhakar Kushwaha3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, 196ddd8a080SPrabhakar KushwahaBLOCK_SIZE=0x00014000 197ddd8a080SPrabhakar Kushwaha 198ddd8a080SPrabhakar Kushwahanand write <rcw image in memory> 0 <size of rcw image> 199ddd8a080SPrabhakar Kushwahanand write <u-boot image in memory> 80000 <size of u-boot image> 200ddd8a080SPrabhakar Kushwaha 201ddd8a080SPrabhakar KushwahaNotice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image 202ddd8a080SPrabhakar Kushwahato match board NAND device with 4KB/page, block size 512KB. 203ddd8a080SPrabhakar Kushwaha 204ddd8a080SPrabhakar KushwahaMMU Translation Tables 205ddd8a080SPrabhakar Kushwaha====================== 206ddd8a080SPrabhakar Kushwaha 207ddd8a080SPrabhakar Kushwaha(1) Early MMU Tables: 208ddd8a080SPrabhakar Kushwaha 209ddd8a080SPrabhakar Kushwaha Level 0 Level 1 Level 2 210ddd8a080SPrabhakar Kushwaha------------------ ------------------ ------------------ 211ddd8a080SPrabhakar Kushwaha| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 212ddd8a080SPrabhakar Kushwaha------------------ ------------------ ------------------ 213ddd8a080SPrabhakar Kushwaha| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 214ddd8a080SPrabhakar Kushwaha------------------ | ------------------ ------------------ 215ddd8a080SPrabhakar Kushwaha| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 216ddd8a080SPrabhakar Kushwaha------------------ | ------------------ ------------------ 217ddd8a080SPrabhakar Kushwaha | | 0x00_c000_0000 | | 0x00_0060_0000 | 218ddd8a080SPrabhakar Kushwaha | ------------------ ------------------ 219ddd8a080SPrabhakar Kushwaha | | 0x01_0000_0000 | | 0x00_0080_0000 | 220ddd8a080SPrabhakar Kushwaha | ------------------ ------------------ 221ddd8a080SPrabhakar Kushwaha | ... ... 222ddd8a080SPrabhakar Kushwaha | ------------------ 223ddd8a080SPrabhakar Kushwaha | | 0x05_8000_0000 | --| 224ddd8a080SPrabhakar Kushwaha | ------------------ | 225ddd8a080SPrabhakar Kushwaha | | 0x05_c000_0000 | | 226ddd8a080SPrabhakar Kushwaha | ------------------ | 227ddd8a080SPrabhakar Kushwaha | ... | 228ddd8a080SPrabhakar Kushwaha | ------------------ | ------------------ 229ddd8a080SPrabhakar Kushwaha |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | 230ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 231ddd8a080SPrabhakar Kushwaha | 0x80_4000_0000 | | 0x00_3020_0000 | 232ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 233ddd8a080SPrabhakar Kushwaha | 0x80_8000_0000 | | 0x00_3040_0000 | 234ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 235ddd8a080SPrabhakar Kushwaha | 0x80_c000_0000 | | 0x00_3060_0000 | 236ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 237ddd8a080SPrabhakar Kushwaha | 0x81_0000_0000 | | 0x00_3080_0000 | 238ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 239ddd8a080SPrabhakar Kushwaha ... ... 240ddd8a080SPrabhakar Kushwaha 241ddd8a080SPrabhakar Kushwaha(2) Final MMU Tables: 242ddd8a080SPrabhakar Kushwaha 243ddd8a080SPrabhakar Kushwaha Level 0 Level 1 Level 2 244ddd8a080SPrabhakar Kushwaha------------------ ------------------ ------------------ 245ddd8a080SPrabhakar Kushwaha| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 246ddd8a080SPrabhakar Kushwaha------------------ ------------------ ------------------ 247ddd8a080SPrabhakar Kushwaha| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 248ddd8a080SPrabhakar Kushwaha------------------ | ------------------ ------------------ 249ddd8a080SPrabhakar Kushwaha| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 250ddd8a080SPrabhakar Kushwaha------------------ | ------------------ ------------------ 251ddd8a080SPrabhakar Kushwaha | | 0x00_c000_0000 | | 0x00_0060_0000 | 252ddd8a080SPrabhakar Kushwaha | ------------------ ------------------ 253ddd8a080SPrabhakar Kushwaha | | 0x01_0000_0000 | | 0x00_0080_0000 | 254ddd8a080SPrabhakar Kushwaha | ------------------ ------------------ 255ddd8a080SPrabhakar Kushwaha | ... ... 256ddd8a080SPrabhakar Kushwaha | ------------------ 257ddd8a080SPrabhakar Kushwaha | | 0x08_0000_0000 | --| 258ddd8a080SPrabhakar Kushwaha | ------------------ | 259ddd8a080SPrabhakar Kushwaha | | 0x08_4000_0000 | | 260ddd8a080SPrabhakar Kushwaha | ------------------ | 261ddd8a080SPrabhakar Kushwaha | ... | 262ddd8a080SPrabhakar Kushwaha | ------------------ | ------------------ 263ddd8a080SPrabhakar Kushwaha |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | 264ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 265ddd8a080SPrabhakar Kushwaha | 0x80_4000_0000 | | 0x08_0020_0000 | 266ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 267ddd8a080SPrabhakar Kushwaha | 0x80_8000_0000 | | 0x08_0040_0000 | 268ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 269ddd8a080SPrabhakar Kushwaha | 0x80_c000_0000 | | 0x08_0060_0000 | 270ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 271ddd8a080SPrabhakar Kushwaha | 0x81_0000_0000 | | 0x08_0080_0000 | 272ddd8a080SPrabhakar Kushwaha ------------------ ------------------ 273ddd8a080SPrabhakar Kushwaha ... ... 274ddd8a080SPrabhakar Kushwaha 275ddd8a080SPrabhakar Kushwaha 276ddd8a080SPrabhakar KushwahaDPAA2 commands to manage Management Complex (MC) 277ddd8a080SPrabhakar Kushwaha------------------------------------------------ 278ddd8a080SPrabhakar KushwahaDPAA2 commands has been introduced to manage Management Complex 279ddd8a080SPrabhakar Kushwaha(MC). These commands are used to start mc, aiop and apply DPL 280ddd8a080SPrabhakar Kushwahafrom u-boot command prompt. 281ddd8a080SPrabhakar Kushwaha 282ddd8a080SPrabhakar KushwahaPlease note Management complex Firmware(MC), DPL and DPC are no 283ddd8a080SPrabhakar Kushwahamore deployed during u-boot boot-sequence. 284ddd8a080SPrabhakar Kushwaha 285ddd8a080SPrabhakar KushwahaCommands: 286ddd8a080SPrabhakar Kushwahaa) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 287ddd8a080SPrabhakar Kushwahab) fsl_mc apply DPL <DPL_addr> - Apply DPL file 288ddd8a080SPrabhakar Kushwahac) fsl_mc start aiop <FW_addr> - Start AIOP 289ddd8a080SPrabhakar Kushwaha 290ddd8a080SPrabhakar KushwahaHow to use commands :- 291ddd8a080SPrabhakar Kushwaha1. Command sequence for u-boot ethernet: 292ddd8a080SPrabhakar Kushwaha a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 293ddd8a080SPrabhakar Kushwaha b) DPMAC net-devices are now available for use 294ddd8a080SPrabhakar Kushwaha 295ddd8a080SPrabhakar Kushwaha Example- 296ddd8a080SPrabhakar Kushwaha Assumption: MC firmware, DPL and DPC dtb is already programmed 297ddd8a080SPrabhakar Kushwaha on NOR flash. 298ddd8a080SPrabhakar Kushwaha 299ddd8a080SPrabhakar Kushwaha => fsl_mc start mc 580300000 580800000 300ddd8a080SPrabhakar Kushwaha => setenv ethact DPMAC1@xgmii 301ddd8a080SPrabhakar Kushwaha => ping $serverip 302ddd8a080SPrabhakar Kushwaha 303ddd8a080SPrabhakar Kushwaha2. Command sequence for Linux boot: 304ddd8a080SPrabhakar Kushwaha a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 305ddd8a080SPrabhakar Kushwaha b) fsl_mc apply DPL <DPL_addr> - Apply DPL file 306ddd8a080SPrabhakar Kushwaha c) No DPMAC net-devices are available for use in u-boot 307ddd8a080SPrabhakar Kushwaha d) boot Linux 308ddd8a080SPrabhakar Kushwaha 309ddd8a080SPrabhakar Kushwaha Example- 310ddd8a080SPrabhakar Kushwaha Assumption: MC firmware, DPL and DPC dtb is already programmed 311ddd8a080SPrabhakar Kushwaha on NOR flash. 312ddd8a080SPrabhakar Kushwaha 313ddd8a080SPrabhakar Kushwaha => fsl_mc start mc 580300000 580800000 314ddd8a080SPrabhakar Kushwaha => setenv ethact DPMAC1@xgmii 315ddd8a080SPrabhakar Kushwaha => tftp a0000000 kernel.itb 316ddd8a080SPrabhakar Kushwaha => fsl_mc apply dpl 580700000 317ddd8a080SPrabhakar Kushwaha => bootm a0000000 318ddd8a080SPrabhakar Kushwaha 319ddd8a080SPrabhakar Kushwaha3. Command sequence for AIOP boot: 320ddd8a080SPrabhakar Kushwaha a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 321ddd8a080SPrabhakar Kushwaha b) fsl_mc start aiop <FW_addr> - Start AIOP 322ddd8a080SPrabhakar Kushwaha c) fsl_mc apply DPL <DPL_addr> - Apply DPL file 323ddd8a080SPrabhakar Kushwaha d) No DPMAC net-devices are availabe for use in u-boot 324ddd8a080SPrabhakar Kushwaha Please note actual AIOP start will happen during DPL parsing of 325ddd8a080SPrabhakar Kushwaha Management complex 326ddd8a080SPrabhakar Kushwaha 327ddd8a080SPrabhakar Kushwaha Example- 328ddd8a080SPrabhakar Kushwaha Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already 329ddd8a080SPrabhakar Kushwaha programmed on NOR flash. 330ddd8a080SPrabhakar Kushwaha 331ddd8a080SPrabhakar Kushwaha => fsl_mc start mc 580300000 580800000 332ddd8a080SPrabhakar Kushwaha => fsl_mc start aiop 0x580900000 333ddd8a080SPrabhakar Kushwaha => setenv ethact DPMAC1@xgmii 334ddd8a080SPrabhakar Kushwaha => fsl_mc apply dpl 580700000 335ddd8a080SPrabhakar Kushwaha 336ddd8a080SPrabhakar KushwahaErrata A009635 337ddd8a080SPrabhakar Kushwaha--------------- 338ddd8a080SPrabhakar KushwahaIf the core runs at higher than x3 speed of the platform, there is 339ddd8a080SPrabhakar Kushwahapossiblity about sev instruction to getting missed by other cores. 340ddd8a080SPrabhakar KushwahaThis is because of SoC Run Control block may not able to sample 341ddd8a080SPrabhakar Kushwahathe EVENTI(Sev) signals. 342ddd8a080SPrabhakar Kushwaha 343ddd8a080SPrabhakar KushwahaWorkaround: Configure Run Control and EPU to periodically send out EVENTI signals to 344ddd8a080SPrabhakar Kushwahawake up A57 cores 345ddd8a080SPrabhakar Kushwaha 346ddd8a080SPrabhakar KushwahaErrata workaround uses Env variable "a009635_interval_val". It uses decimal 347ddd8a080SPrabhakar Kushwahavalue. 348ddd8a080SPrabhakar Kushwaha- Default value of env variable is platform clock (MHz) 349ddd8a080SPrabhakar Kushwaha 350ddd8a080SPrabhakar Kushwaha- User can modify default value by updating the env variable 351ddd8a080SPrabhakar Kushwaha setenv a009635_interval_val 600; saveenv; 352ddd8a080SPrabhakar Kushwaha It configure platform clock as 600 MHz 353ddd8a080SPrabhakar Kushwaha 354ddd8a080SPrabhakar Kushwaha- Env variable as 0 signifies no workaround 355