1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/io.h> 11 #include <linux/errno.h> 12 #include <asm/system.h> 13 #include <asm/armv8/mmu.h> 14 #include <asm/io.h> 15 #include <asm/arch/fsl_serdes.h> 16 #include <asm/arch/soc.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/speed.h> 19 #include <fsl_immap.h> 20 #include <asm/arch/mp.h> 21 #include <efi_loader.h> 22 #include <fm_eth.h> 23 #include <fsl-mc/fsl_mc.h> 24 #ifdef CONFIG_FSL_ESDHC 25 #include <fsl_esdhc.h> 26 #endif 27 #include <asm/armv8/sec_firmware.h> 28 #ifdef CONFIG_SYS_FSL_DDR 29 #include <fsl_ddr.h> 30 #endif 31 #include <asm/arch/clock.h> 32 #include <hwconfig.h> 33 #include <fsl_qbman.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 struct mm_region *mem_map = early_map; 38 39 void cpu_name(char *name) 40 { 41 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 42 unsigned int i, svr, ver; 43 44 svr = gur_in32(&gur->svr); 45 ver = SVR_SOC_VER(svr); 46 47 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 48 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { 49 strcpy(name, cpu_type_list[i].name); 50 51 if (IS_E_PROCESSOR(svr)) 52 strcat(name, "E"); 53 54 sprintf(name + strlen(name), " Rev%d.%d", 55 SVR_MAJ(svr), SVR_MIN(svr)); 56 break; 57 } 58 59 if (i == ARRAY_SIZE(cpu_type_list)) 60 strcpy(name, "unknown"); 61 } 62 63 #ifndef CONFIG_SYS_DCACHE_OFF 64 /* 65 * To start MMU before DDR is available, we create MMU table in SRAM. 66 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three 67 * levels of translation tables here to cover 40-bit address space. 68 * We use 4KB granule size, with 40 bits physical address, T0SZ=24 69 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. 70 * Note, the debug print in cache_v8.c is not usable for debugging 71 * these early MMU tables because UART is not yet available. 72 */ 73 static inline void early_mmu_setup(void) 74 { 75 unsigned int el = current_el(); 76 77 /* global data is already setup, no allocation yet */ 78 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; 79 gd->arch.tlb_fillptr = gd->arch.tlb_addr; 80 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; 81 82 /* Create early page tables */ 83 setup_pgtables(); 84 85 /* point TTBR to the new table */ 86 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 87 get_tcr(el, NULL, NULL) & 88 ~(TCR_ORGN_MASK | TCR_IRGN_MASK), 89 MEMORY_ATTRIBUTES); 90 91 set_sctlr(get_sctlr() | CR_M); 92 } 93 94 static void fix_pcie_mmu_map(void) 95 { 96 #ifdef CONFIG_ARCH_LS2080A 97 unsigned int i; 98 u32 svr, ver; 99 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 100 101 svr = gur_in32(&gur->svr); 102 ver = SVR_SOC_VER(svr); 103 104 /* Fix PCIE base and size for LS2088A */ 105 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || 106 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || 107 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { 108 for (i = 0; i < ARRAY_SIZE(final_map); i++) { 109 switch (final_map[i].phys) { 110 case CONFIG_SYS_PCIE1_PHYS_ADDR: 111 final_map[i].phys = 0x2000000000ULL; 112 final_map[i].virt = 0x2000000000ULL; 113 final_map[i].size = 0x800000000ULL; 114 break; 115 case CONFIG_SYS_PCIE2_PHYS_ADDR: 116 final_map[i].phys = 0x2800000000ULL; 117 final_map[i].virt = 0x2800000000ULL; 118 final_map[i].size = 0x800000000ULL; 119 break; 120 case CONFIG_SYS_PCIE3_PHYS_ADDR: 121 final_map[i].phys = 0x3000000000ULL; 122 final_map[i].virt = 0x3000000000ULL; 123 final_map[i].size = 0x800000000ULL; 124 break; 125 case CONFIG_SYS_PCIE4_PHYS_ADDR: 126 final_map[i].phys = 0x3800000000ULL; 127 final_map[i].virt = 0x3800000000ULL; 128 final_map[i].size = 0x800000000ULL; 129 break; 130 default: 131 break; 132 } 133 } 134 } 135 #endif 136 } 137 138 /* 139 * The final tables look similar to early tables, but different in detail. 140 * These tables are in DRAM. Sub tables are added to enable cache for 141 * QBMan and OCRAM. 142 * 143 * Put the MMU table in secure memory if gd->arch.secure_ram is valid. 144 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. 145 */ 146 static inline void final_mmu_setup(void) 147 { 148 u64 tlb_addr_save = gd->arch.tlb_addr; 149 unsigned int el = current_el(); 150 int index; 151 152 /* fix the final_map before filling in the block entries */ 153 fix_pcie_mmu_map(); 154 155 mem_map = final_map; 156 157 /* Update mapping for DDR to actual size */ 158 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { 159 /* 160 * Find the entry for DDR mapping and update the address and 161 * size. Zero-sized mapping will be skipped when creating MMU 162 * table. 163 */ 164 switch (final_map[index].virt) { 165 case CONFIG_SYS_FSL_DRAM_BASE1: 166 final_map[index].virt = gd->bd->bi_dram[0].start; 167 final_map[index].phys = gd->bd->bi_dram[0].start; 168 final_map[index].size = gd->bd->bi_dram[0].size; 169 break; 170 #ifdef CONFIG_SYS_FSL_DRAM_BASE2 171 case CONFIG_SYS_FSL_DRAM_BASE2: 172 #if (CONFIG_NR_DRAM_BANKS >= 2) 173 final_map[index].virt = gd->bd->bi_dram[1].start; 174 final_map[index].phys = gd->bd->bi_dram[1].start; 175 final_map[index].size = gd->bd->bi_dram[1].size; 176 #else 177 final_map[index].size = 0; 178 #endif 179 break; 180 #endif 181 #ifdef CONFIG_SYS_FSL_DRAM_BASE3 182 case CONFIG_SYS_FSL_DRAM_BASE3: 183 #if (CONFIG_NR_DRAM_BANKS >= 3) 184 final_map[index].virt = gd->bd->bi_dram[2].start; 185 final_map[index].phys = gd->bd->bi_dram[2].start; 186 final_map[index].size = gd->bd->bi_dram[2].size; 187 #else 188 final_map[index].size = 0; 189 #endif 190 break; 191 #endif 192 default: 193 break; 194 } 195 } 196 197 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 198 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 199 if (el == 3) { 200 /* 201 * Only use gd->arch.secure_ram if the address is 202 * recalculated. Align to 4KB for MMU table. 203 */ 204 /* put page tables in secure ram */ 205 index = ARRAY_SIZE(final_map) - 2; 206 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; 207 final_map[index].virt = gd->arch.secure_ram & ~0x3; 208 final_map[index].phys = final_map[index].virt; 209 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; 210 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; 211 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; 212 tlb_addr_save = gd->arch.tlb_addr; 213 } else { 214 /* Use allocated (board_f.c) memory for TLB */ 215 tlb_addr_save = gd->arch.tlb_allocated; 216 gd->arch.tlb_addr = tlb_addr_save; 217 } 218 } 219 #endif 220 221 /* Reset the fill ptr */ 222 gd->arch.tlb_fillptr = tlb_addr_save; 223 224 /* Create normal system page tables */ 225 setup_pgtables(); 226 227 /* Create emergency page tables */ 228 gd->arch.tlb_addr = gd->arch.tlb_fillptr; 229 gd->arch.tlb_emerg = gd->arch.tlb_addr; 230 setup_pgtables(); 231 gd->arch.tlb_addr = tlb_addr_save; 232 233 /* Disable cache and MMU */ 234 dcache_disable(); /* TLBs are invalidated */ 235 invalidate_icache_all(); 236 237 /* point TTBR to the new table */ 238 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), 239 MEMORY_ATTRIBUTES); 240 241 set_sctlr(get_sctlr() | CR_M); 242 } 243 244 u64 get_page_table_size(void) 245 { 246 return 0x10000; 247 } 248 249 int arch_cpu_init(void) 250 { 251 /* 252 * This function is called before U-Boot relocates itself to speed up 253 * on system running. It is not necessary to run if performance is not 254 * critical. Skip if MMU is already enabled by SPL or other means. 255 */ 256 if (get_sctlr() & CR_M) 257 return 0; 258 259 icache_enable(); 260 __asm_invalidate_dcache_all(); 261 __asm_invalidate_tlb_all(); 262 early_mmu_setup(); 263 set_sctlr(get_sctlr() | CR_C); 264 return 0; 265 } 266 267 void mmu_setup(void) 268 { 269 final_mmu_setup(); 270 } 271 272 /* 273 * This function is called from common/board_r.c. 274 * It recreates MMU table in main memory. 275 */ 276 void enable_caches(void) 277 { 278 mmu_setup(); 279 __asm_invalidate_tlb_all(); 280 icache_enable(); 281 dcache_enable(); 282 } 283 #endif 284 285 u32 initiator_type(u32 cluster, int init_id) 286 { 287 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 288 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 289 u32 type = 0; 290 291 type = gur_in32(&gur->tp_ityp[idx]); 292 if (type & TP_ITYP_AV) 293 return type; 294 295 return 0; 296 } 297 298 u32 cpu_pos_mask(void) 299 { 300 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 301 int i = 0; 302 u32 cluster, type, mask = 0; 303 304 do { 305 int j; 306 307 cluster = gur_in32(&gur->tp_cluster[i].lower); 308 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 309 type = initiator_type(cluster, j); 310 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) 311 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); 312 } 313 i++; 314 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 315 316 return mask; 317 } 318 319 u32 cpu_mask(void) 320 { 321 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 322 int i = 0, count = 0; 323 u32 cluster, type, mask = 0; 324 325 do { 326 int j; 327 328 cluster = gur_in32(&gur->tp_cluster[i].lower); 329 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 330 type = initiator_type(cluster, j); 331 if (type) { 332 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 333 mask |= 1 << count; 334 count++; 335 } 336 } 337 i++; 338 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 339 340 return mask; 341 } 342 343 /* 344 * Return the number of cores on this SOC. 345 */ 346 int cpu_numcores(void) 347 { 348 return hweight32(cpu_mask()); 349 } 350 351 int fsl_qoriq_core_to_cluster(unsigned int core) 352 { 353 struct ccsr_gur __iomem *gur = 354 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 355 int i = 0, count = 0; 356 u32 cluster; 357 358 do { 359 int j; 360 361 cluster = gur_in32(&gur->tp_cluster[i].lower); 362 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 363 if (initiator_type(cluster, j)) { 364 if (count == core) 365 return i; 366 count++; 367 } 368 } 369 i++; 370 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 371 372 return -1; /* cannot identify the cluster */ 373 } 374 375 u32 fsl_qoriq_core_to_type(unsigned int core) 376 { 377 struct ccsr_gur __iomem *gur = 378 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 379 int i = 0, count = 0; 380 u32 cluster, type; 381 382 do { 383 int j; 384 385 cluster = gur_in32(&gur->tp_cluster[i].lower); 386 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 387 type = initiator_type(cluster, j); 388 if (type) { 389 if (count == core) 390 return type; 391 count++; 392 } 393 } 394 i++; 395 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 396 397 return -1; /* cannot identify the cluster */ 398 } 399 400 #ifndef CONFIG_FSL_LSCH3 401 uint get_svr(void) 402 { 403 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 404 405 return gur_in32(&gur->svr); 406 } 407 #endif 408 409 #ifdef CONFIG_DISPLAY_CPUINFO 410 int print_cpuinfo(void) 411 { 412 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 413 struct sys_info sysinfo; 414 char buf[32]; 415 unsigned int i, core; 416 u32 type, rcw, svr = gur_in32(&gur->svr); 417 418 puts("SoC: "); 419 420 cpu_name(buf); 421 printf(" %s (0x%x)\n", buf, svr); 422 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 423 get_sys_info(&sysinfo); 424 puts("Clock Configuration:"); 425 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { 426 if (!(i % 3)) 427 puts("\n "); 428 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); 429 printf("CPU%d(%s):%-4s MHz ", core, 430 type == TY_ITYP_VER_A7 ? "A7 " : 431 (type == TY_ITYP_VER_A53 ? "A53" : 432 (type == TY_ITYP_VER_A57 ? "A57" : 433 (type == TY_ITYP_VER_A72 ? "A72" : " "))), 434 strmhz(buf, sysinfo.freq_processor[core])); 435 } 436 /* Display platform clock as Bus frequency. */ 437 printf("\n Bus: %-4s MHz ", 438 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); 439 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); 440 #ifdef CONFIG_SYS_DPAA_FMAN 441 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); 442 #endif 443 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 444 if (soc_has_dp_ddr()) { 445 printf(" DP-DDR: %-4s MT/s", 446 strmhz(buf, sysinfo.freq_ddrbus2)); 447 } 448 #endif 449 puts("\n"); 450 451 /* 452 * Display the RCW, so that no one gets confused as to what RCW 453 * we're actually using for this boot. 454 */ 455 puts("Reset Configuration Word (RCW):"); 456 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 457 rcw = gur_in32(&gur->rcwsr[i]); 458 if ((i % 4) == 0) 459 printf("\n %08x:", i * 4); 460 printf(" %08x", rcw); 461 } 462 puts("\n"); 463 464 return 0; 465 } 466 #endif 467 468 #ifdef CONFIG_FSL_ESDHC 469 int cpu_mmc_init(bd_t *bis) 470 { 471 return fsl_esdhc_mmc_init(bis); 472 } 473 #endif 474 475 int cpu_eth_init(bd_t *bis) 476 { 477 int error = 0; 478 479 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 480 error = fsl_mc_ldpaa_init(bis); 481 #endif 482 #ifdef CONFIG_FMAN_ENET 483 fm_standard_init(bis); 484 #endif 485 return error; 486 } 487 488 static inline int check_psci(void) 489 { 490 unsigned int psci_ver; 491 492 psci_ver = sec_firmware_support_psci_version(); 493 if (psci_ver == PSCI_INVALID_VER) 494 return 1; 495 496 return 0; 497 } 498 499 static void config_core_prefetch(void) 500 { 501 char *buf = NULL; 502 char buffer[HWCONFIG_BUFFER_SIZE]; 503 const char *prefetch_arg = NULL; 504 size_t arglen; 505 unsigned int mask; 506 struct pt_regs regs; 507 508 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) 509 buf = buffer; 510 511 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", 512 &arglen, buf); 513 514 if (prefetch_arg) { 515 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff; 516 if (mask & 0x1) { 517 printf("Core0 prefetch can't be disabled\n"); 518 return; 519 } 520 521 #define SIP_PREFETCH_DISABLE_64 0xC200FF13 522 regs.regs[0] = SIP_PREFETCH_DISABLE_64; 523 regs.regs[1] = mask; 524 smc_call(®s); 525 526 if (regs.regs[0]) 527 printf("Prefetch disable config failed for mask "); 528 else 529 printf("Prefetch disable config passed for mask "); 530 printf("0x%x\n", mask); 531 } 532 } 533 534 int arch_early_init_r(void) 535 { 536 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 537 u32 svr_dev_id; 538 /* 539 * erratum A009635 is valid only for LS2080A SoC and 540 * its personalitiesi 541 */ 542 svr_dev_id = get_svr(); 543 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) 544 erratum_a009635(); 545 #endif 546 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) 547 erratum_a009942_check_cpo(); 548 #endif 549 if (check_psci()) { 550 debug("PSCI: PSCI does not exist.\n"); 551 552 /* if PSCI does not exist, boot secondary cores here */ 553 if (fsl_layerscape_wake_seconday_cores()) 554 printf("Did not wake secondary cores\n"); 555 } 556 557 #ifdef CONFIG_SYS_FSL_HAS_RGMII 558 fsl_rgmii_init(); 559 #endif 560 561 config_core_prefetch(); 562 563 #ifdef CONFIG_SYS_HAS_SERDES 564 fsl_serdes_init(); 565 #endif 566 #ifdef CONFIG_FMAN_ENET 567 fman_enet_init(); 568 #endif 569 #ifdef CONFIG_SYS_DPAA_QBMAN 570 setup_qbman_portals(); 571 #endif 572 return 0; 573 } 574 575 int timer_init(void) 576 { 577 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; 578 #ifdef CONFIG_FSL_LSCH3 579 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; 580 #endif 581 #ifdef CONFIG_ARCH_LS2080A 582 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; 583 u32 svr_dev_id; 584 #endif 585 #ifdef COUNTER_FREQUENCY_REAL 586 unsigned long cntfrq = COUNTER_FREQUENCY_REAL; 587 588 /* Update with accurate clock frequency */ 589 if (current_el() == 3) 590 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); 591 #endif 592 593 #ifdef CONFIG_FSL_LSCH3 594 /* Enable timebase for all clusters. 595 * It is safe to do so even some clusters are not enabled. 596 */ 597 out_le32(cltbenr, 0xf); 598 #endif 599 600 #ifdef CONFIG_ARCH_LS2080A 601 /* 602 * In certain Layerscape SoCs, the clock for each core's 603 * has an enable bit in the PMU Physical Core Time Base Enable 604 * Register (PCTBENR), which allows the watchdog to operate. 605 */ 606 setbits_le32(pctbenr, 0xff); 607 /* 608 * For LS2080A SoC and its personalities, timer controller 609 * offset is different 610 */ 611 svr_dev_id = get_svr(); 612 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) 613 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; 614 615 #endif 616 617 /* Enable clock for timer 618 * This is a global setting. 619 */ 620 out_le32(cntcr, 0x1); 621 622 return 0; 623 } 624 625 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; 626 627 void __efi_runtime reset_cpu(ulong addr) 628 { 629 u32 val; 630 631 /* Raise RESET_REQ_B */ 632 val = scfg_in32(rstcr); 633 val |= 0x02; 634 scfg_out32(rstcr, val); 635 } 636 637 #ifdef CONFIG_EFI_LOADER 638 639 void __efi_runtime EFIAPI efi_reset_system( 640 enum efi_reset_type reset_type, 641 efi_status_t reset_status, 642 unsigned long data_size, void *reset_data) 643 { 644 switch (reset_type) { 645 case EFI_RESET_COLD: 646 case EFI_RESET_WARM: 647 reset_cpu(0); 648 break; 649 case EFI_RESET_SHUTDOWN: 650 /* Nothing we can do */ 651 break; 652 } 653 654 while (1) { } 655 } 656 657 void efi_reset_system_init(void) 658 { 659 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); 660 } 661 662 #endif 663 664 /* 665 * Calculate reserved memory with given memory bank 666 * Return aligned memory size on success 667 * Return (ram_size + needed size) for failure 668 */ 669 phys_size_t board_reserve_ram_top(phys_size_t ram_size) 670 { 671 phys_size_t ram_top = ram_size; 672 673 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 674 ram_top = mc_get_dram_block_size(); 675 if (ram_top > ram_size) 676 return ram_size + ram_top; 677 678 ram_top = ram_size - ram_top; 679 /* The start address of MC reserved memory needs to be aligned. */ 680 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); 681 #endif 682 683 return ram_size - ram_top; 684 } 685 686 phys_size_t get_effective_memsize(void) 687 { 688 phys_size_t ea_size, rem = 0; 689 690 /* 691 * For ARMv8 SoCs, DDR memory is split into two or three regions. The 692 * first region is 2GB space at 0x8000_0000. Secure memory needs to 693 * allocated from first region. If the memory extends to the second 694 * region (or the third region if applicable), Management Complex (MC) 695 * memory should be put into the highest region, i.e. the end of DDR 696 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so 697 * U-Boot doesn't relocate itself into higher address. Should DDR be 698 * configured to skip the first region, this function needs to be 699 * adjusted. 700 */ 701 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 702 ea_size = CONFIG_MAX_MEM_MAPPED; 703 rem = gd->ram_size - ea_size; 704 } else { 705 ea_size = gd->ram_size; 706 } 707 708 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 709 /* Check if we have enough space for secure memory */ 710 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) 711 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 712 else 713 printf("Error: No enough space for secure memory.\n"); 714 #endif 715 /* Check if we have enough memory for MC */ 716 if (rem < board_reserve_ram_top(rem)) { 717 /* Not enough memory in high region to reserve */ 718 if (ea_size > board_reserve_ram_top(ea_size)) 719 ea_size -= board_reserve_ram_top(ea_size); 720 else 721 printf("Error: No enough space for reserved memory.\n"); 722 } 723 724 return ea_size; 725 } 726 727 int dram_init_banksize(void) 728 { 729 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 730 phys_size_t dp_ddr_size; 731 #endif 732 733 /* 734 * gd->ram_size has the total size of DDR memory, less reserved secure 735 * memory. The DDR extends from low region to high region(s) presuming 736 * no hole is created with DDR configuration. gd->arch.secure_ram tracks 737 * the location of secure memory. gd->arch.resv_ram tracks the location 738 * of reserved memory for Management Complex (MC). Because gd->ram_size 739 * is reduced by this function if secure memory is reserved, checking 740 * gd->arch.secure_ram should be done to avoid running it repeatedly. 741 */ 742 743 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 744 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 745 debug("No need to run again, skip %s\n", __func__); 746 747 return 0; 748 } 749 #endif 750 751 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 752 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { 753 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; 754 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 755 gd->bd->bi_dram[1].size = gd->ram_size - 756 CONFIG_SYS_DDR_BLOCK1_SIZE; 757 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 758 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { 759 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; 760 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - 761 CONFIG_SYS_DDR_BLOCK2_SIZE; 762 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; 763 } 764 #endif 765 } else { 766 gd->bd->bi_dram[0].size = gd->ram_size; 767 } 768 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 769 if (gd->bd->bi_dram[0].size > 770 CONFIG_SYS_MEM_RESERVE_SECURE) { 771 gd->bd->bi_dram[0].size -= 772 CONFIG_SYS_MEM_RESERVE_SECURE; 773 gd->arch.secure_ram = gd->bd->bi_dram[0].start + 774 gd->bd->bi_dram[0].size; 775 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 776 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 777 } 778 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ 779 780 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 781 /* Assign memory for MC */ 782 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 783 if (gd->bd->bi_dram[2].size >= 784 board_reserve_ram_top(gd->bd->bi_dram[2].size)) { 785 gd->arch.resv_ram = gd->bd->bi_dram[2].start + 786 gd->bd->bi_dram[2].size - 787 board_reserve_ram_top(gd->bd->bi_dram[2].size); 788 } else 789 #endif 790 { 791 if (gd->bd->bi_dram[1].size >= 792 board_reserve_ram_top(gd->bd->bi_dram[1].size)) { 793 gd->arch.resv_ram = gd->bd->bi_dram[1].start + 794 gd->bd->bi_dram[1].size - 795 board_reserve_ram_top(gd->bd->bi_dram[1].size); 796 } else if (gd->bd->bi_dram[0].size > 797 board_reserve_ram_top(gd->bd->bi_dram[0].size)) { 798 gd->arch.resv_ram = gd->bd->bi_dram[0].start + 799 gd->bd->bi_dram[0].size - 800 board_reserve_ram_top(gd->bd->bi_dram[0].size); 801 } 802 } 803 #endif /* CONFIG_FSL_MC_ENET */ 804 805 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 806 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 807 #error "This SoC shouldn't have DP DDR" 808 #endif 809 if (soc_has_dp_ddr()) { 810 /* initialize DP-DDR here */ 811 puts("DP-DDR: "); 812 /* 813 * DDR controller use 0 as the base address for binding. 814 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 815 */ 816 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, 817 CONFIG_DP_DDR_CTRL, 818 CONFIG_DP_DDR_NUM_CTRLS, 819 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, 820 NULL, NULL, NULL); 821 if (dp_ddr_size) { 822 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; 823 gd->bd->bi_dram[2].size = dp_ddr_size; 824 } else { 825 puts("Not detected"); 826 } 827 } 828 #endif 829 830 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 831 debug("%s is called. gd->ram_size is reduced to %lu\n", 832 __func__, (ulong)gd->ram_size); 833 #endif 834 835 return 0; 836 } 837 838 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) 839 void efi_add_known_memory(void) 840 { 841 int i; 842 phys_addr_t ram_start, start; 843 phys_size_t ram_size; 844 u64 pages; 845 846 /* Add RAM */ 847 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 848 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 849 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 850 #error "This SoC shouldn't have DP DDR" 851 #endif 852 if (i == 2) 853 continue; /* skip DP-DDR */ 854 #endif 855 ram_start = gd->bd->bi_dram[i].start; 856 ram_size = gd->bd->bi_dram[i].size; 857 #ifdef CONFIG_RESV_RAM 858 if (gd->arch.resv_ram >= ram_start && 859 gd->arch.resv_ram < ram_start + ram_size) 860 ram_size = gd->arch.resv_ram - ram_start; 861 #endif 862 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; 863 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; 864 865 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, 866 false); 867 } 868 } 869 #endif 870 871 /* 872 * Before DDR size is known, early MMU table have DDR mapped as device memory 873 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" 874 * needs to be set for these mappings. 875 * If a special case configures DDR with holes in the mapping, the holes need 876 * to be marked as invalid. This is not implemented in this function. 877 */ 878 void update_early_mmu_table(void) 879 { 880 if (!gd->arch.tlb_addr) 881 return; 882 883 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { 884 mmu_change_region_attr( 885 CONFIG_SYS_SDRAM_BASE, 886 gd->ram_size, 887 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 888 PTE_BLOCK_OUTER_SHARE | 889 PTE_BLOCK_NS | 890 PTE_TYPE_VALID); 891 } else { 892 mmu_change_region_attr( 893 CONFIG_SYS_SDRAM_BASE, 894 CONFIG_SYS_DDR_BLOCK1_SIZE, 895 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 896 PTE_BLOCK_OUTER_SHARE | 897 PTE_BLOCK_NS | 898 PTE_TYPE_VALID); 899 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 900 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE 901 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" 902 #endif 903 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > 904 CONFIG_SYS_DDR_BLOCK2_SIZE) { 905 mmu_change_region_attr( 906 CONFIG_SYS_DDR_BLOCK2_BASE, 907 CONFIG_SYS_DDR_BLOCK2_SIZE, 908 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 909 PTE_BLOCK_OUTER_SHARE | 910 PTE_BLOCK_NS | 911 PTE_TYPE_VALID); 912 mmu_change_region_attr( 913 CONFIG_SYS_DDR_BLOCK3_BASE, 914 gd->ram_size - 915 CONFIG_SYS_DDR_BLOCK1_SIZE - 916 CONFIG_SYS_DDR_BLOCK2_SIZE, 917 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 918 PTE_BLOCK_OUTER_SHARE | 919 PTE_BLOCK_NS | 920 PTE_TYPE_VALID); 921 } else 922 #endif 923 { 924 mmu_change_region_attr( 925 CONFIG_SYS_DDR_BLOCK2_BASE, 926 gd->ram_size - 927 CONFIG_SYS_DDR_BLOCK1_SIZE, 928 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 929 PTE_BLOCK_OUTER_SHARE | 930 PTE_BLOCK_NS | 931 PTE_TYPE_VALID); 932 } 933 } 934 } 935 936 __weak int dram_init(void) 937 { 938 fsl_initdram(); 939 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 940 /* This will break-before-make MMU for DDR */ 941 update_early_mmu_table(); 942 #endif 943 944 return 0; 945 } 946