1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <asm/io.h> 10 #include <linux/errno.h> 11 #include <asm/system.h> 12 #include <asm/armv8/mmu.h> 13 #include <asm/io.h> 14 #include <asm/arch/fsl_serdes.h> 15 #include <asm/arch/soc.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/speed.h> 18 #include <asm/arch/mp.h> 19 #include <efi_loader.h> 20 #include <fm_eth.h> 21 #include <fsl-mc/fsl_mc.h> 22 #ifdef CONFIG_FSL_ESDHC 23 #include <fsl_esdhc.h> 24 #endif 25 #include <asm/armv8/sec_firmware.h> 26 #ifdef CONFIG_SYS_FSL_DDR 27 #include <fsl_ddr.h> 28 #endif 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 struct mm_region *mem_map = early_map; 33 34 void cpu_name(char *name) 35 { 36 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 37 unsigned int i, svr, ver; 38 39 svr = gur_in32(&gur->svr); 40 ver = SVR_SOC_VER(svr); 41 42 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 43 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { 44 strcpy(name, cpu_type_list[i].name); 45 46 if (IS_E_PROCESSOR(svr)) 47 strcat(name, "E"); 48 49 sprintf(name + strlen(name), " Rev%d.%d", 50 SVR_MAJ(svr), SVR_MIN(svr)); 51 break; 52 } 53 54 if (i == ARRAY_SIZE(cpu_type_list)) 55 strcpy(name, "unknown"); 56 } 57 58 #ifndef CONFIG_SYS_DCACHE_OFF 59 /* 60 * To start MMU before DDR is available, we create MMU table in SRAM. 61 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three 62 * levels of translation tables here to cover 40-bit address space. 63 * We use 4KB granule size, with 40 bits physical address, T0SZ=24 64 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. 65 * Note, the debug print in cache_v8.c is not usable for debugging 66 * these early MMU tables because UART is not yet available. 67 */ 68 static inline void early_mmu_setup(void) 69 { 70 unsigned int el = current_el(); 71 72 /* global data is already setup, no allocation yet */ 73 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; 74 gd->arch.tlb_fillptr = gd->arch.tlb_addr; 75 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; 76 77 /* Create early page tables */ 78 setup_pgtables(); 79 80 /* point TTBR to the new table */ 81 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 82 get_tcr(el, NULL, NULL) & 83 ~(TCR_ORGN_MASK | TCR_IRGN_MASK), 84 MEMORY_ATTRIBUTES); 85 86 set_sctlr(get_sctlr() | CR_M); 87 } 88 89 static void fix_pcie_mmu_map(void) 90 { 91 #ifdef CONFIG_ARCH_LS2080A 92 unsigned int i; 93 u32 svr, ver; 94 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 95 96 svr = gur_in32(&gur->svr); 97 ver = SVR_SOC_VER(svr); 98 99 /* Fix PCIE base and size for LS2088A */ 100 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || 101 (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { 102 for (i = 0; i < ARRAY_SIZE(final_map); i++) { 103 switch (final_map[i].phys) { 104 case CONFIG_SYS_PCIE1_PHYS_ADDR: 105 final_map[i].phys = 0x2000000000ULL; 106 final_map[i].virt = 0x2000000000ULL; 107 final_map[i].size = 0x800000000ULL; 108 break; 109 case CONFIG_SYS_PCIE2_PHYS_ADDR: 110 final_map[i].phys = 0x2800000000ULL; 111 final_map[i].virt = 0x2800000000ULL; 112 final_map[i].size = 0x800000000ULL; 113 break; 114 case CONFIG_SYS_PCIE3_PHYS_ADDR: 115 final_map[i].phys = 0x3000000000ULL; 116 final_map[i].virt = 0x3000000000ULL; 117 final_map[i].size = 0x800000000ULL; 118 break; 119 case CONFIG_SYS_PCIE4_PHYS_ADDR: 120 final_map[i].phys = 0x3800000000ULL; 121 final_map[i].virt = 0x3800000000ULL; 122 final_map[i].size = 0x800000000ULL; 123 break; 124 default: 125 break; 126 } 127 } 128 } 129 #endif 130 } 131 132 /* 133 * The final tables look similar to early tables, but different in detail. 134 * These tables are in DRAM. Sub tables are added to enable cache for 135 * QBMan and OCRAM. 136 * 137 * Put the MMU table in secure memory if gd->arch.secure_ram is valid. 138 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. 139 */ 140 static inline void final_mmu_setup(void) 141 { 142 u64 tlb_addr_save = gd->arch.tlb_addr; 143 unsigned int el = current_el(); 144 int index; 145 146 /* fix the final_map before filling in the block entries */ 147 fix_pcie_mmu_map(); 148 149 mem_map = final_map; 150 151 /* Update mapping for DDR to actual size */ 152 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { 153 /* 154 * Find the entry for DDR mapping and update the address and 155 * size. Zero-sized mapping will be skipped when creating MMU 156 * table. 157 */ 158 switch (final_map[index].virt) { 159 case CONFIG_SYS_FSL_DRAM_BASE1: 160 final_map[index].virt = gd->bd->bi_dram[0].start; 161 final_map[index].phys = gd->bd->bi_dram[0].start; 162 final_map[index].size = gd->bd->bi_dram[0].size; 163 break; 164 #ifdef CONFIG_SYS_FSL_DRAM_BASE2 165 case CONFIG_SYS_FSL_DRAM_BASE2: 166 #if (CONFIG_NR_DRAM_BANKS >= 2) 167 final_map[index].virt = gd->bd->bi_dram[1].start; 168 final_map[index].phys = gd->bd->bi_dram[1].start; 169 final_map[index].size = gd->bd->bi_dram[1].size; 170 #else 171 final_map[index].size = 0; 172 #endif 173 break; 174 #endif 175 #ifdef CONFIG_SYS_FSL_DRAM_BASE3 176 case CONFIG_SYS_FSL_DRAM_BASE3: 177 #if (CONFIG_NR_DRAM_BANKS >= 3) 178 final_map[index].virt = gd->bd->bi_dram[2].start; 179 final_map[index].phys = gd->bd->bi_dram[2].start; 180 final_map[index].size = gd->bd->bi_dram[2].size; 181 #else 182 final_map[index].size = 0; 183 #endif 184 break; 185 #endif 186 default: 187 break; 188 } 189 } 190 191 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 192 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 193 if (el == 3) { 194 /* 195 * Only use gd->arch.secure_ram if the address is 196 * recalculated. Align to 4KB for MMU table. 197 */ 198 /* put page tables in secure ram */ 199 index = ARRAY_SIZE(final_map) - 2; 200 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; 201 final_map[index].virt = gd->arch.secure_ram & ~0x3; 202 final_map[index].phys = final_map[index].virt; 203 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; 204 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; 205 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; 206 tlb_addr_save = gd->arch.tlb_addr; 207 } else { 208 /* Use allocated (board_f.c) memory for TLB */ 209 tlb_addr_save = gd->arch.tlb_allocated; 210 gd->arch.tlb_addr = tlb_addr_save; 211 } 212 } 213 #endif 214 215 /* Reset the fill ptr */ 216 gd->arch.tlb_fillptr = tlb_addr_save; 217 218 /* Create normal system page tables */ 219 setup_pgtables(); 220 221 /* Create emergency page tables */ 222 gd->arch.tlb_addr = gd->arch.tlb_fillptr; 223 gd->arch.tlb_emerg = gd->arch.tlb_addr; 224 setup_pgtables(); 225 gd->arch.tlb_addr = tlb_addr_save; 226 227 /* Disable cache and MMU */ 228 dcache_disable(); /* TLBs are invalidated */ 229 invalidate_icache_all(); 230 231 /* point TTBR to the new table */ 232 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), 233 MEMORY_ATTRIBUTES); 234 235 set_sctlr(get_sctlr() | CR_M); 236 } 237 238 u64 get_page_table_size(void) 239 { 240 return 0x10000; 241 } 242 243 int arch_cpu_init(void) 244 { 245 icache_enable(); 246 __asm_invalidate_dcache_all(); 247 __asm_invalidate_tlb_all(); 248 early_mmu_setup(); 249 set_sctlr(get_sctlr() | CR_C); 250 return 0; 251 } 252 253 void mmu_setup(void) 254 { 255 final_mmu_setup(); 256 } 257 258 /* 259 * This function is called from common/board_r.c. 260 * It recreates MMU table in main memory. 261 */ 262 void enable_caches(void) 263 { 264 mmu_setup(); 265 __asm_invalidate_tlb_all(); 266 icache_enable(); 267 dcache_enable(); 268 } 269 #endif 270 271 u32 initiator_type(u32 cluster, int init_id) 272 { 273 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 274 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 275 u32 type = 0; 276 277 type = gur_in32(&gur->tp_ityp[idx]); 278 if (type & TP_ITYP_AV) 279 return type; 280 281 return 0; 282 } 283 284 u32 cpu_pos_mask(void) 285 { 286 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 287 int i = 0; 288 u32 cluster, type, mask = 0; 289 290 do { 291 int j; 292 293 cluster = gur_in32(&gur->tp_cluster[i].lower); 294 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 295 type = initiator_type(cluster, j); 296 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) 297 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); 298 } 299 i++; 300 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 301 302 return mask; 303 } 304 305 u32 cpu_mask(void) 306 { 307 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 308 int i = 0, count = 0; 309 u32 cluster, type, mask = 0; 310 311 do { 312 int j; 313 314 cluster = gur_in32(&gur->tp_cluster[i].lower); 315 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 316 type = initiator_type(cluster, j); 317 if (type) { 318 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 319 mask |= 1 << count; 320 count++; 321 } 322 } 323 i++; 324 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 325 326 return mask; 327 } 328 329 /* 330 * Return the number of cores on this SOC. 331 */ 332 int cpu_numcores(void) 333 { 334 return hweight32(cpu_mask()); 335 } 336 337 int fsl_qoriq_core_to_cluster(unsigned int core) 338 { 339 struct ccsr_gur __iomem *gur = 340 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 341 int i = 0, count = 0; 342 u32 cluster; 343 344 do { 345 int j; 346 347 cluster = gur_in32(&gur->tp_cluster[i].lower); 348 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 349 if (initiator_type(cluster, j)) { 350 if (count == core) 351 return i; 352 count++; 353 } 354 } 355 i++; 356 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 357 358 return -1; /* cannot identify the cluster */ 359 } 360 361 u32 fsl_qoriq_core_to_type(unsigned int core) 362 { 363 struct ccsr_gur __iomem *gur = 364 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 365 int i = 0, count = 0; 366 u32 cluster, type; 367 368 do { 369 int j; 370 371 cluster = gur_in32(&gur->tp_cluster[i].lower); 372 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 373 type = initiator_type(cluster, j); 374 if (type) { 375 if (count == core) 376 return type; 377 count++; 378 } 379 } 380 i++; 381 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 382 383 return -1; /* cannot identify the cluster */ 384 } 385 386 #ifndef CONFIG_FSL_LSCH3 387 uint get_svr(void) 388 { 389 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 390 391 return gur_in32(&gur->svr); 392 } 393 #endif 394 395 #ifdef CONFIG_DISPLAY_CPUINFO 396 int print_cpuinfo(void) 397 { 398 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 399 struct sys_info sysinfo; 400 char buf[32]; 401 unsigned int i, core; 402 u32 type, rcw, svr = gur_in32(&gur->svr); 403 404 puts("SoC: "); 405 406 cpu_name(buf); 407 printf(" %s (0x%x)\n", buf, svr); 408 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 409 get_sys_info(&sysinfo); 410 puts("Clock Configuration:"); 411 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { 412 if (!(i % 3)) 413 puts("\n "); 414 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); 415 printf("CPU%d(%s):%-4s MHz ", core, 416 type == TY_ITYP_VER_A7 ? "A7 " : 417 (type == TY_ITYP_VER_A53 ? "A53" : 418 (type == TY_ITYP_VER_A57 ? "A57" : 419 (type == TY_ITYP_VER_A72 ? "A72" : " "))), 420 strmhz(buf, sysinfo.freq_processor[core])); 421 } 422 /* Display platform clock as Bus frequency. */ 423 printf("\n Bus: %-4s MHz ", 424 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); 425 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); 426 #ifdef CONFIG_SYS_DPAA_FMAN 427 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); 428 #endif 429 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 430 if (soc_has_dp_ddr()) { 431 printf(" DP-DDR: %-4s MT/s", 432 strmhz(buf, sysinfo.freq_ddrbus2)); 433 } 434 #endif 435 puts("\n"); 436 437 /* 438 * Display the RCW, so that no one gets confused as to what RCW 439 * we're actually using for this boot. 440 */ 441 puts("Reset Configuration Word (RCW):"); 442 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 443 rcw = gur_in32(&gur->rcwsr[i]); 444 if ((i % 4) == 0) 445 printf("\n %08x:", i * 4); 446 printf(" %08x", rcw); 447 } 448 puts("\n"); 449 450 return 0; 451 } 452 #endif 453 454 #ifdef CONFIG_FSL_ESDHC 455 int cpu_mmc_init(bd_t *bis) 456 { 457 return fsl_esdhc_mmc_init(bis); 458 } 459 #endif 460 461 int cpu_eth_init(bd_t *bis) 462 { 463 int error = 0; 464 465 #ifdef CONFIG_FSL_MC_ENET 466 error = fsl_mc_ldpaa_init(bis); 467 #endif 468 #ifdef CONFIG_FMAN_ENET 469 fm_standard_init(bis); 470 #endif 471 return error; 472 } 473 474 static inline int check_psci(void) 475 { 476 unsigned int psci_ver; 477 478 psci_ver = sec_firmware_support_psci_version(); 479 if (psci_ver == PSCI_INVALID_VER) 480 return 1; 481 482 return 0; 483 } 484 485 int arch_early_init_r(void) 486 { 487 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 488 u32 svr_dev_id; 489 /* 490 * erratum A009635 is valid only for LS2080A SoC and 491 * its personalitiesi 492 */ 493 svr_dev_id = get_svr() >> 16; 494 if (svr_dev_id == SVR_DEV_LS2080A) 495 erratum_a009635(); 496 #endif 497 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) 498 erratum_a009942_check_cpo(); 499 #endif 500 if (check_psci()) { 501 debug("PSCI: PSCI does not exist.\n"); 502 503 /* if PSCI does not exist, boot secondary cores here */ 504 if (fsl_layerscape_wake_seconday_cores()) 505 printf("Did not wake secondary cores\n"); 506 } 507 508 #ifdef CONFIG_SYS_HAS_SERDES 509 fsl_serdes_init(); 510 #endif 511 #ifdef CONFIG_FMAN_ENET 512 fman_enet_init(); 513 #endif 514 return 0; 515 } 516 517 int timer_init(void) 518 { 519 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; 520 #ifdef CONFIG_FSL_LSCH3 521 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; 522 #endif 523 #ifdef CONFIG_ARCH_LS2080A 524 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; 525 u32 svr_dev_id; 526 #endif 527 #ifdef COUNTER_FREQUENCY_REAL 528 unsigned long cntfrq = COUNTER_FREQUENCY_REAL; 529 530 /* Update with accurate clock frequency */ 531 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); 532 #endif 533 534 #ifdef CONFIG_FSL_LSCH3 535 /* Enable timebase for all clusters. 536 * It is safe to do so even some clusters are not enabled. 537 */ 538 out_le32(cltbenr, 0xf); 539 #endif 540 541 #ifdef CONFIG_ARCH_LS2080A 542 /* 543 * In certain Layerscape SoCs, the clock for each core's 544 * has an enable bit in the PMU Physical Core Time Base Enable 545 * Register (PCTBENR), which allows the watchdog to operate. 546 */ 547 setbits_le32(pctbenr, 0xff); 548 /* 549 * For LS2080A SoC and its personalities, timer controller 550 * offset is different 551 */ 552 svr_dev_id = get_svr() >> 16; 553 if (svr_dev_id == SVR_DEV_LS2080A) 554 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; 555 556 #endif 557 558 /* Enable clock for timer 559 * This is a global setting. 560 */ 561 out_le32(cntcr, 0x1); 562 563 return 0; 564 } 565 566 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; 567 568 void __efi_runtime reset_cpu(ulong addr) 569 { 570 u32 val; 571 572 /* Raise RESET_REQ_B */ 573 val = scfg_in32(rstcr); 574 val |= 0x02; 575 scfg_out32(rstcr, val); 576 } 577 578 #ifdef CONFIG_EFI_LOADER 579 580 void __efi_runtime EFIAPI efi_reset_system( 581 enum efi_reset_type reset_type, 582 efi_status_t reset_status, 583 unsigned long data_size, void *reset_data) 584 { 585 switch (reset_type) { 586 case EFI_RESET_COLD: 587 case EFI_RESET_WARM: 588 reset_cpu(0); 589 break; 590 case EFI_RESET_SHUTDOWN: 591 /* Nothing we can do */ 592 break; 593 } 594 595 while (1) { } 596 } 597 598 void efi_reset_system_init(void) 599 { 600 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); 601 } 602 603 #endif 604 605 phys_size_t board_reserve_ram_top(phys_size_t ram_size) 606 { 607 phys_size_t ram_top = ram_size; 608 609 #ifdef CONFIG_FSL_MC_ENET 610 /* The start address of MC reserved memory needs to be aligned. */ 611 ram_top -= mc_get_dram_block_size(); 612 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); 613 #endif 614 615 return ram_size - ram_top; 616 } 617 618 phys_size_t get_effective_memsize(void) 619 { 620 phys_size_t ea_size, rem = 0; 621 622 /* 623 * For ARMv8 SoCs, DDR memory is split into two or three regions. The 624 * first region is 2GB space at 0x8000_0000. If the memory extends to 625 * the second region (or the third region if applicable), the secure 626 * memory and Management Complex (MC) memory should be put into the 627 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED 628 * is set to the size of first region so U-Boot doesn't relocate itself 629 * into higher address. Should DDR be configured to skip the first 630 * region, this function needs to be adjusted. 631 */ 632 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 633 ea_size = CONFIG_MAX_MEM_MAPPED; 634 rem = gd->ram_size - ea_size; 635 } else { 636 ea_size = gd->ram_size; 637 } 638 639 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 640 /* Check if we have enough space for secure memory */ 641 if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { 642 rem -= CONFIG_SYS_MEM_RESERVE_SECURE; 643 } else { 644 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { 645 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 646 rem = 0; /* Presume MC requires more memory */ 647 } else { 648 printf("Error: No enough space for secure memory.\n"); 649 } 650 } 651 #endif 652 /* Check if we have enough memory for MC */ 653 if (rem < board_reserve_ram_top(rem)) { 654 /* Not enough memory in high region to reserve */ 655 if (ea_size > board_reserve_ram_top(rem)) 656 ea_size -= board_reserve_ram_top(rem); 657 else 658 printf("Error: No enough space for reserved memory.\n"); 659 } 660 661 return ea_size; 662 } 663 664 int dram_init_banksize(void) 665 { 666 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 667 phys_size_t dp_ddr_size; 668 #endif 669 670 /* 671 * gd->ram_size has the total size of DDR memory, less reserved secure 672 * memory. The DDR extends from low region to high region(s) presuming 673 * no hole is created with DDR configuration. gd->arch.secure_ram tracks 674 * the location of secure memory. gd->arch.resv_ram tracks the location 675 * of reserved memory for Management Complex (MC). 676 */ 677 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 678 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { 679 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; 680 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 681 gd->bd->bi_dram[1].size = gd->ram_size - 682 CONFIG_SYS_DDR_BLOCK1_SIZE; 683 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 684 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { 685 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; 686 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - 687 CONFIG_SYS_DDR_BLOCK2_SIZE; 688 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; 689 } 690 #endif 691 } else { 692 gd->bd->bi_dram[0].size = gd->ram_size; 693 } 694 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 695 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 696 if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 697 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; 698 gd->arch.secure_ram = gd->bd->bi_dram[2].start + 699 gd->bd->bi_dram[2].size; 700 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 701 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 702 } else 703 #endif 704 { 705 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 706 gd->bd->bi_dram[1].size -= 707 CONFIG_SYS_MEM_RESERVE_SECURE; 708 gd->arch.secure_ram = gd->bd->bi_dram[1].start + 709 gd->bd->bi_dram[1].size; 710 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 711 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 712 } else if (gd->bd->bi_dram[0].size > 713 CONFIG_SYS_MEM_RESERVE_SECURE) { 714 gd->bd->bi_dram[0].size -= 715 CONFIG_SYS_MEM_RESERVE_SECURE; 716 gd->arch.secure_ram = gd->bd->bi_dram[0].start + 717 gd->bd->bi_dram[0].size; 718 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 719 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 720 } 721 } 722 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ 723 724 #ifdef CONFIG_FSL_MC_ENET 725 /* Assign memory for MC */ 726 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 727 if (gd->bd->bi_dram[2].size >= 728 board_reserve_ram_top(gd->bd->bi_dram[2].size)) { 729 gd->arch.resv_ram = gd->bd->bi_dram[2].start + 730 gd->bd->bi_dram[2].size - 731 board_reserve_ram_top(gd->bd->bi_dram[2].size); 732 } else 733 #endif 734 { 735 if (gd->bd->bi_dram[1].size >= 736 board_reserve_ram_top(gd->bd->bi_dram[1].size)) { 737 gd->arch.resv_ram = gd->bd->bi_dram[1].start + 738 gd->bd->bi_dram[1].size - 739 board_reserve_ram_top(gd->bd->bi_dram[1].size); 740 } else if (gd->bd->bi_dram[0].size > 741 board_reserve_ram_top(gd->bd->bi_dram[0].size)) { 742 gd->arch.resv_ram = gd->bd->bi_dram[0].start + 743 gd->bd->bi_dram[0].size - 744 board_reserve_ram_top(gd->bd->bi_dram[0].size); 745 } 746 } 747 #endif /* CONFIG_FSL_MC_ENET */ 748 749 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 750 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 751 #error "This SoC shouldn't have DP DDR" 752 #endif 753 if (soc_has_dp_ddr()) { 754 /* initialize DP-DDR here */ 755 puts("DP-DDR: "); 756 /* 757 * DDR controller use 0 as the base address for binding. 758 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 759 */ 760 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, 761 CONFIG_DP_DDR_CTRL, 762 CONFIG_DP_DDR_NUM_CTRLS, 763 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, 764 NULL, NULL, NULL); 765 if (dp_ddr_size) { 766 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; 767 gd->bd->bi_dram[2].size = dp_ddr_size; 768 } else { 769 puts("Not detected"); 770 } 771 } 772 #endif 773 774 return 0; 775 } 776 777 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) 778 void efi_add_known_memory(void) 779 { 780 int i; 781 phys_addr_t ram_start, start; 782 phys_size_t ram_size; 783 u64 pages; 784 785 /* Add RAM */ 786 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 787 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 788 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 789 #error "This SoC shouldn't have DP DDR" 790 #endif 791 if (i == 2) 792 continue; /* skip DP-DDR */ 793 #endif 794 ram_start = gd->bd->bi_dram[i].start; 795 ram_size = gd->bd->bi_dram[i].size; 796 #ifdef CONFIG_RESV_RAM 797 if (gd->arch.resv_ram >= ram_start && 798 gd->arch.resv_ram < ram_start + ram_size) 799 ram_size = gd->arch.resv_ram - ram_start; 800 #endif 801 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; 802 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; 803 804 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, 805 false); 806 } 807 } 808 #endif 809 810 /* 811 * Before DDR size is known, early MMU table have DDR mapped as device memory 812 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" 813 * needs to be set for these mappings. 814 * If a special case configures DDR with holes in the mapping, the holes need 815 * to be marked as invalid. This is not implemented in this function. 816 */ 817 void update_early_mmu_table(void) 818 { 819 if (!gd->arch.tlb_addr) 820 return; 821 822 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { 823 mmu_change_region_attr( 824 CONFIG_SYS_SDRAM_BASE, 825 gd->ram_size, 826 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 827 PTE_BLOCK_OUTER_SHARE | 828 PTE_BLOCK_NS | 829 PTE_TYPE_VALID); 830 } else { 831 mmu_change_region_attr( 832 CONFIG_SYS_SDRAM_BASE, 833 CONFIG_SYS_DDR_BLOCK1_SIZE, 834 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 835 PTE_BLOCK_OUTER_SHARE | 836 PTE_BLOCK_NS | 837 PTE_TYPE_VALID); 838 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 839 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE 840 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" 841 #endif 842 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > 843 CONFIG_SYS_DDR_BLOCK2_SIZE) { 844 mmu_change_region_attr( 845 CONFIG_SYS_DDR_BLOCK2_BASE, 846 CONFIG_SYS_DDR_BLOCK2_SIZE, 847 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 848 PTE_BLOCK_OUTER_SHARE | 849 PTE_BLOCK_NS | 850 PTE_TYPE_VALID); 851 mmu_change_region_attr( 852 CONFIG_SYS_DDR_BLOCK3_BASE, 853 gd->ram_size - 854 CONFIG_SYS_DDR_BLOCK1_SIZE - 855 CONFIG_SYS_DDR_BLOCK2_SIZE, 856 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 857 PTE_BLOCK_OUTER_SHARE | 858 PTE_BLOCK_NS | 859 PTE_TYPE_VALID); 860 } else 861 #endif 862 { 863 mmu_change_region_attr( 864 CONFIG_SYS_DDR_BLOCK2_BASE, 865 gd->ram_size - 866 CONFIG_SYS_DDR_BLOCK1_SIZE, 867 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 868 PTE_BLOCK_OUTER_SHARE | 869 PTE_BLOCK_NS | 870 PTE_TYPE_VALID); 871 } 872 } 873 } 874 875 __weak int dram_init(void) 876 { 877 fsl_initdram(); 878 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 879 /* This will break-before-make MMU for DDR */ 880 update_early_mmu_table(); 881 #endif 882 883 return 0; 884 } 885