1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/io.h> 11 #include <linux/errno.h> 12 #include <asm/system.h> 13 #include <asm/armv8/mmu.h> 14 #include <asm/io.h> 15 #include <asm/arch/fsl_serdes.h> 16 #include <asm/arch/soc.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/speed.h> 19 #include <fsl_immap.h> 20 #include <asm/arch/mp.h> 21 #include <efi_loader.h> 22 #include <fm_eth.h> 23 #include <fsl-mc/fsl_mc.h> 24 #ifdef CONFIG_FSL_ESDHC 25 #include <fsl_esdhc.h> 26 #endif 27 #include <asm/armv8/sec_firmware.h> 28 #ifdef CONFIG_SYS_FSL_DDR 29 #include <fsl_ddr.h> 30 #endif 31 #include <asm/arch/clock.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 struct mm_region *mem_map = early_map; 36 37 void cpu_name(char *name) 38 { 39 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 40 unsigned int i, svr, ver; 41 42 svr = gur_in32(&gur->svr); 43 ver = SVR_SOC_VER(svr); 44 45 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 46 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { 47 strcpy(name, cpu_type_list[i].name); 48 49 if (IS_E_PROCESSOR(svr)) 50 strcat(name, "E"); 51 52 sprintf(name + strlen(name), " Rev%d.%d", 53 SVR_MAJ(svr), SVR_MIN(svr)); 54 break; 55 } 56 57 if (i == ARRAY_SIZE(cpu_type_list)) 58 strcpy(name, "unknown"); 59 } 60 61 #ifndef CONFIG_SYS_DCACHE_OFF 62 /* 63 * To start MMU before DDR is available, we create MMU table in SRAM. 64 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three 65 * levels of translation tables here to cover 40-bit address space. 66 * We use 4KB granule size, with 40 bits physical address, T0SZ=24 67 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. 68 * Note, the debug print in cache_v8.c is not usable for debugging 69 * these early MMU tables because UART is not yet available. 70 */ 71 static inline void early_mmu_setup(void) 72 { 73 unsigned int el = current_el(); 74 75 /* global data is already setup, no allocation yet */ 76 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; 77 gd->arch.tlb_fillptr = gd->arch.tlb_addr; 78 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; 79 80 /* Create early page tables */ 81 setup_pgtables(); 82 83 /* point TTBR to the new table */ 84 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 85 get_tcr(el, NULL, NULL) & 86 ~(TCR_ORGN_MASK | TCR_IRGN_MASK), 87 MEMORY_ATTRIBUTES); 88 89 set_sctlr(get_sctlr() | CR_M); 90 } 91 92 static void fix_pcie_mmu_map(void) 93 { 94 #ifdef CONFIG_ARCH_LS2080A 95 unsigned int i; 96 u32 svr, ver; 97 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 98 99 svr = gur_in32(&gur->svr); 100 ver = SVR_SOC_VER(svr); 101 102 /* Fix PCIE base and size for LS2088A */ 103 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || 104 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || 105 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { 106 for (i = 0; i < ARRAY_SIZE(final_map); i++) { 107 switch (final_map[i].phys) { 108 case CONFIG_SYS_PCIE1_PHYS_ADDR: 109 final_map[i].phys = 0x2000000000ULL; 110 final_map[i].virt = 0x2000000000ULL; 111 final_map[i].size = 0x800000000ULL; 112 break; 113 case CONFIG_SYS_PCIE2_PHYS_ADDR: 114 final_map[i].phys = 0x2800000000ULL; 115 final_map[i].virt = 0x2800000000ULL; 116 final_map[i].size = 0x800000000ULL; 117 break; 118 case CONFIG_SYS_PCIE3_PHYS_ADDR: 119 final_map[i].phys = 0x3000000000ULL; 120 final_map[i].virt = 0x3000000000ULL; 121 final_map[i].size = 0x800000000ULL; 122 break; 123 case CONFIG_SYS_PCIE4_PHYS_ADDR: 124 final_map[i].phys = 0x3800000000ULL; 125 final_map[i].virt = 0x3800000000ULL; 126 final_map[i].size = 0x800000000ULL; 127 break; 128 default: 129 break; 130 } 131 } 132 } 133 #endif 134 } 135 136 /* 137 * The final tables look similar to early tables, but different in detail. 138 * These tables are in DRAM. Sub tables are added to enable cache for 139 * QBMan and OCRAM. 140 * 141 * Put the MMU table in secure memory if gd->arch.secure_ram is valid. 142 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. 143 */ 144 static inline void final_mmu_setup(void) 145 { 146 u64 tlb_addr_save = gd->arch.tlb_addr; 147 unsigned int el = current_el(); 148 int index; 149 150 /* fix the final_map before filling in the block entries */ 151 fix_pcie_mmu_map(); 152 153 mem_map = final_map; 154 155 /* Update mapping for DDR to actual size */ 156 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { 157 /* 158 * Find the entry for DDR mapping and update the address and 159 * size. Zero-sized mapping will be skipped when creating MMU 160 * table. 161 */ 162 switch (final_map[index].virt) { 163 case CONFIG_SYS_FSL_DRAM_BASE1: 164 final_map[index].virt = gd->bd->bi_dram[0].start; 165 final_map[index].phys = gd->bd->bi_dram[0].start; 166 final_map[index].size = gd->bd->bi_dram[0].size; 167 break; 168 #ifdef CONFIG_SYS_FSL_DRAM_BASE2 169 case CONFIG_SYS_FSL_DRAM_BASE2: 170 #if (CONFIG_NR_DRAM_BANKS >= 2) 171 final_map[index].virt = gd->bd->bi_dram[1].start; 172 final_map[index].phys = gd->bd->bi_dram[1].start; 173 final_map[index].size = gd->bd->bi_dram[1].size; 174 #else 175 final_map[index].size = 0; 176 #endif 177 break; 178 #endif 179 #ifdef CONFIG_SYS_FSL_DRAM_BASE3 180 case CONFIG_SYS_FSL_DRAM_BASE3: 181 #if (CONFIG_NR_DRAM_BANKS >= 3) 182 final_map[index].virt = gd->bd->bi_dram[2].start; 183 final_map[index].phys = gd->bd->bi_dram[2].start; 184 final_map[index].size = gd->bd->bi_dram[2].size; 185 #else 186 final_map[index].size = 0; 187 #endif 188 break; 189 #endif 190 default: 191 break; 192 } 193 } 194 195 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 196 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 197 if (el == 3) { 198 /* 199 * Only use gd->arch.secure_ram if the address is 200 * recalculated. Align to 4KB for MMU table. 201 */ 202 /* put page tables in secure ram */ 203 index = ARRAY_SIZE(final_map) - 2; 204 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; 205 final_map[index].virt = gd->arch.secure_ram & ~0x3; 206 final_map[index].phys = final_map[index].virt; 207 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; 208 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; 209 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; 210 tlb_addr_save = gd->arch.tlb_addr; 211 } else { 212 /* Use allocated (board_f.c) memory for TLB */ 213 tlb_addr_save = gd->arch.tlb_allocated; 214 gd->arch.tlb_addr = tlb_addr_save; 215 } 216 } 217 #endif 218 219 /* Reset the fill ptr */ 220 gd->arch.tlb_fillptr = tlb_addr_save; 221 222 /* Create normal system page tables */ 223 setup_pgtables(); 224 225 /* Create emergency page tables */ 226 gd->arch.tlb_addr = gd->arch.tlb_fillptr; 227 gd->arch.tlb_emerg = gd->arch.tlb_addr; 228 setup_pgtables(); 229 gd->arch.tlb_addr = tlb_addr_save; 230 231 /* Disable cache and MMU */ 232 dcache_disable(); /* TLBs are invalidated */ 233 invalidate_icache_all(); 234 235 /* point TTBR to the new table */ 236 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), 237 MEMORY_ATTRIBUTES); 238 239 set_sctlr(get_sctlr() | CR_M); 240 } 241 242 u64 get_page_table_size(void) 243 { 244 return 0x10000; 245 } 246 247 int arch_cpu_init(void) 248 { 249 /* 250 * This function is called before U-Boot relocates itself to speed up 251 * on system running. It is not necessary to run if performance is not 252 * critical. Skip if MMU is already enabled by SPL or other means. 253 */ 254 if (get_sctlr() & CR_M) 255 return 0; 256 257 icache_enable(); 258 __asm_invalidate_dcache_all(); 259 __asm_invalidate_tlb_all(); 260 early_mmu_setup(); 261 set_sctlr(get_sctlr() | CR_C); 262 return 0; 263 } 264 265 void mmu_setup(void) 266 { 267 final_mmu_setup(); 268 } 269 270 /* 271 * This function is called from common/board_r.c. 272 * It recreates MMU table in main memory. 273 */ 274 void enable_caches(void) 275 { 276 mmu_setup(); 277 __asm_invalidate_tlb_all(); 278 icache_enable(); 279 dcache_enable(); 280 } 281 #endif 282 283 u32 initiator_type(u32 cluster, int init_id) 284 { 285 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 286 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 287 u32 type = 0; 288 289 type = gur_in32(&gur->tp_ityp[idx]); 290 if (type & TP_ITYP_AV) 291 return type; 292 293 return 0; 294 } 295 296 u32 cpu_pos_mask(void) 297 { 298 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 299 int i = 0; 300 u32 cluster, type, mask = 0; 301 302 do { 303 int j; 304 305 cluster = gur_in32(&gur->tp_cluster[i].lower); 306 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 307 type = initiator_type(cluster, j); 308 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) 309 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); 310 } 311 i++; 312 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 313 314 return mask; 315 } 316 317 u32 cpu_mask(void) 318 { 319 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 320 int i = 0, count = 0; 321 u32 cluster, type, mask = 0; 322 323 do { 324 int j; 325 326 cluster = gur_in32(&gur->tp_cluster[i].lower); 327 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 328 type = initiator_type(cluster, j); 329 if (type) { 330 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 331 mask |= 1 << count; 332 count++; 333 } 334 } 335 i++; 336 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 337 338 return mask; 339 } 340 341 /* 342 * Return the number of cores on this SOC. 343 */ 344 int cpu_numcores(void) 345 { 346 return hweight32(cpu_mask()); 347 } 348 349 int fsl_qoriq_core_to_cluster(unsigned int core) 350 { 351 struct ccsr_gur __iomem *gur = 352 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 353 int i = 0, count = 0; 354 u32 cluster; 355 356 do { 357 int j; 358 359 cluster = gur_in32(&gur->tp_cluster[i].lower); 360 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 361 if (initiator_type(cluster, j)) { 362 if (count == core) 363 return i; 364 count++; 365 } 366 } 367 i++; 368 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 369 370 return -1; /* cannot identify the cluster */ 371 } 372 373 u32 fsl_qoriq_core_to_type(unsigned int core) 374 { 375 struct ccsr_gur __iomem *gur = 376 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 377 int i = 0, count = 0; 378 u32 cluster, type; 379 380 do { 381 int j; 382 383 cluster = gur_in32(&gur->tp_cluster[i].lower); 384 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 385 type = initiator_type(cluster, j); 386 if (type) { 387 if (count == core) 388 return type; 389 count++; 390 } 391 } 392 i++; 393 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 394 395 return -1; /* cannot identify the cluster */ 396 } 397 398 #ifndef CONFIG_FSL_LSCH3 399 uint get_svr(void) 400 { 401 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 402 403 return gur_in32(&gur->svr); 404 } 405 #endif 406 407 #ifdef CONFIG_DISPLAY_CPUINFO 408 int print_cpuinfo(void) 409 { 410 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 411 struct sys_info sysinfo; 412 char buf[32]; 413 unsigned int i, core; 414 u32 type, rcw, svr = gur_in32(&gur->svr); 415 416 puts("SoC: "); 417 418 cpu_name(buf); 419 printf(" %s (0x%x)\n", buf, svr); 420 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 421 get_sys_info(&sysinfo); 422 puts("Clock Configuration:"); 423 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { 424 if (!(i % 3)) 425 puts("\n "); 426 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); 427 printf("CPU%d(%s):%-4s MHz ", core, 428 type == TY_ITYP_VER_A7 ? "A7 " : 429 (type == TY_ITYP_VER_A53 ? "A53" : 430 (type == TY_ITYP_VER_A57 ? "A57" : 431 (type == TY_ITYP_VER_A72 ? "A72" : " "))), 432 strmhz(buf, sysinfo.freq_processor[core])); 433 } 434 /* Display platform clock as Bus frequency. */ 435 printf("\n Bus: %-4s MHz ", 436 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); 437 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); 438 #ifdef CONFIG_SYS_DPAA_FMAN 439 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); 440 #endif 441 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 442 if (soc_has_dp_ddr()) { 443 printf(" DP-DDR: %-4s MT/s", 444 strmhz(buf, sysinfo.freq_ddrbus2)); 445 } 446 #endif 447 puts("\n"); 448 449 /* 450 * Display the RCW, so that no one gets confused as to what RCW 451 * we're actually using for this boot. 452 */ 453 puts("Reset Configuration Word (RCW):"); 454 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 455 rcw = gur_in32(&gur->rcwsr[i]); 456 if ((i % 4) == 0) 457 printf("\n %08x:", i * 4); 458 printf(" %08x", rcw); 459 } 460 puts("\n"); 461 462 return 0; 463 } 464 #endif 465 466 #ifdef CONFIG_FSL_ESDHC 467 int cpu_mmc_init(bd_t *bis) 468 { 469 return fsl_esdhc_mmc_init(bis); 470 } 471 #endif 472 473 int cpu_eth_init(bd_t *bis) 474 { 475 int error = 0; 476 477 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 478 error = fsl_mc_ldpaa_init(bis); 479 #endif 480 #ifdef CONFIG_FMAN_ENET 481 fm_standard_init(bis); 482 #endif 483 return error; 484 } 485 486 static inline int check_psci(void) 487 { 488 unsigned int psci_ver; 489 490 psci_ver = sec_firmware_support_psci_version(); 491 if (psci_ver == PSCI_INVALID_VER) 492 return 1; 493 494 return 0; 495 } 496 497 int arch_early_init_r(void) 498 { 499 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 500 u32 svr_dev_id; 501 /* 502 * erratum A009635 is valid only for LS2080A SoC and 503 * its personalitiesi 504 */ 505 svr_dev_id = get_svr() >> 16; 506 if (svr_dev_id == SVR_DEV_LS2080A) 507 erratum_a009635(); 508 #endif 509 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) 510 erratum_a009942_check_cpo(); 511 #endif 512 if (check_psci()) { 513 debug("PSCI: PSCI does not exist.\n"); 514 515 /* if PSCI does not exist, boot secondary cores here */ 516 if (fsl_layerscape_wake_seconday_cores()) 517 printf("Did not wake secondary cores\n"); 518 } 519 520 #ifdef CONFIG_SYS_FSL_HAS_RGMII 521 fsl_rgmii_init(); 522 #endif 523 524 #ifdef CONFIG_SYS_HAS_SERDES 525 fsl_serdes_init(); 526 #endif 527 #ifdef CONFIG_FMAN_ENET 528 fman_enet_init(); 529 #endif 530 return 0; 531 } 532 533 int timer_init(void) 534 { 535 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; 536 #ifdef CONFIG_FSL_LSCH3 537 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; 538 #endif 539 #ifdef CONFIG_ARCH_LS2080A 540 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; 541 u32 svr_dev_id; 542 #endif 543 #ifdef COUNTER_FREQUENCY_REAL 544 unsigned long cntfrq = COUNTER_FREQUENCY_REAL; 545 546 /* Update with accurate clock frequency */ 547 if (current_el() == 3) 548 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); 549 #endif 550 551 #ifdef CONFIG_FSL_LSCH3 552 /* Enable timebase for all clusters. 553 * It is safe to do so even some clusters are not enabled. 554 */ 555 out_le32(cltbenr, 0xf); 556 #endif 557 558 #ifdef CONFIG_ARCH_LS2080A 559 /* 560 * In certain Layerscape SoCs, the clock for each core's 561 * has an enable bit in the PMU Physical Core Time Base Enable 562 * Register (PCTBENR), which allows the watchdog to operate. 563 */ 564 setbits_le32(pctbenr, 0xff); 565 /* 566 * For LS2080A SoC and its personalities, timer controller 567 * offset is different 568 */ 569 svr_dev_id = get_svr() >> 16; 570 if (svr_dev_id == SVR_DEV_LS2080A) 571 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; 572 573 #endif 574 575 /* Enable clock for timer 576 * This is a global setting. 577 */ 578 out_le32(cntcr, 0x1); 579 580 return 0; 581 } 582 583 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; 584 585 void __efi_runtime reset_cpu(ulong addr) 586 { 587 u32 val; 588 589 /* Raise RESET_REQ_B */ 590 val = scfg_in32(rstcr); 591 val |= 0x02; 592 scfg_out32(rstcr, val); 593 } 594 595 #ifdef CONFIG_EFI_LOADER 596 597 void __efi_runtime EFIAPI efi_reset_system( 598 enum efi_reset_type reset_type, 599 efi_status_t reset_status, 600 unsigned long data_size, void *reset_data) 601 { 602 switch (reset_type) { 603 case EFI_RESET_COLD: 604 case EFI_RESET_WARM: 605 reset_cpu(0); 606 break; 607 case EFI_RESET_SHUTDOWN: 608 /* Nothing we can do */ 609 break; 610 } 611 612 while (1) { } 613 } 614 615 void efi_reset_system_init(void) 616 { 617 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); 618 } 619 620 #endif 621 622 /* 623 * Calculate reserved memory with given memory bank 624 * Return aligned memory size on success 625 * Return (ram_size + needed size) for failure 626 */ 627 phys_size_t board_reserve_ram_top(phys_size_t ram_size) 628 { 629 phys_size_t ram_top = ram_size; 630 631 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 632 ram_top = mc_get_dram_block_size(); 633 if (ram_top > ram_size) 634 return ram_size + ram_top; 635 636 ram_top = ram_size - ram_top; 637 /* The start address of MC reserved memory needs to be aligned. */ 638 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); 639 #endif 640 641 return ram_size - ram_top; 642 } 643 644 phys_size_t get_effective_memsize(void) 645 { 646 phys_size_t ea_size, rem = 0; 647 648 /* 649 * For ARMv8 SoCs, DDR memory is split into two or three regions. The 650 * first region is 2GB space at 0x8000_0000. If the memory extends to 651 * the second region (or the third region if applicable), the secure 652 * memory and Management Complex (MC) memory should be put into the 653 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED 654 * is set to the size of first region so U-Boot doesn't relocate itself 655 * into higher address. Should DDR be configured to skip the first 656 * region, this function needs to be adjusted. 657 */ 658 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 659 ea_size = CONFIG_MAX_MEM_MAPPED; 660 rem = gd->ram_size - ea_size; 661 } else { 662 ea_size = gd->ram_size; 663 } 664 665 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 666 /* Check if we have enough space for secure memory */ 667 if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { 668 rem -= CONFIG_SYS_MEM_RESERVE_SECURE; 669 } else { 670 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { 671 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 672 rem = 0; /* Presume MC requires more memory */ 673 } else { 674 printf("Error: No enough space for secure memory.\n"); 675 } 676 } 677 #endif 678 /* Check if we have enough memory for MC */ 679 if (rem < board_reserve_ram_top(rem)) { 680 /* Not enough memory in high region to reserve */ 681 if (ea_size > board_reserve_ram_top(ea_size)) 682 ea_size -= board_reserve_ram_top(ea_size); 683 else 684 printf("Error: No enough space for reserved memory.\n"); 685 } 686 687 return ea_size; 688 } 689 690 int dram_init_banksize(void) 691 { 692 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 693 phys_size_t dp_ddr_size; 694 #endif 695 696 /* 697 * gd->ram_size has the total size of DDR memory, less reserved secure 698 * memory. The DDR extends from low region to high region(s) presuming 699 * no hole is created with DDR configuration. gd->arch.secure_ram tracks 700 * the location of secure memory. gd->arch.resv_ram tracks the location 701 * of reserved memory for Management Complex (MC). 702 */ 703 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 704 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { 705 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; 706 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 707 gd->bd->bi_dram[1].size = gd->ram_size - 708 CONFIG_SYS_DDR_BLOCK1_SIZE; 709 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 710 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { 711 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; 712 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - 713 CONFIG_SYS_DDR_BLOCK2_SIZE; 714 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; 715 } 716 #endif 717 } else { 718 gd->bd->bi_dram[0].size = gd->ram_size; 719 } 720 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 721 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 722 if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 723 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; 724 gd->arch.secure_ram = gd->bd->bi_dram[2].start + 725 gd->bd->bi_dram[2].size; 726 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 727 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 728 } else 729 #endif 730 { 731 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 732 gd->bd->bi_dram[1].size -= 733 CONFIG_SYS_MEM_RESERVE_SECURE; 734 gd->arch.secure_ram = gd->bd->bi_dram[1].start + 735 gd->bd->bi_dram[1].size; 736 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 737 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 738 } else if (gd->bd->bi_dram[0].size > 739 CONFIG_SYS_MEM_RESERVE_SECURE) { 740 gd->bd->bi_dram[0].size -= 741 CONFIG_SYS_MEM_RESERVE_SECURE; 742 gd->arch.secure_ram = gd->bd->bi_dram[0].start + 743 gd->bd->bi_dram[0].size; 744 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 745 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 746 } 747 } 748 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ 749 750 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 751 /* Assign memory for MC */ 752 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 753 if (gd->bd->bi_dram[2].size >= 754 board_reserve_ram_top(gd->bd->bi_dram[2].size)) { 755 gd->arch.resv_ram = gd->bd->bi_dram[2].start + 756 gd->bd->bi_dram[2].size - 757 board_reserve_ram_top(gd->bd->bi_dram[2].size); 758 } else 759 #endif 760 { 761 if (gd->bd->bi_dram[1].size >= 762 board_reserve_ram_top(gd->bd->bi_dram[1].size)) { 763 gd->arch.resv_ram = gd->bd->bi_dram[1].start + 764 gd->bd->bi_dram[1].size - 765 board_reserve_ram_top(gd->bd->bi_dram[1].size); 766 } else if (gd->bd->bi_dram[0].size > 767 board_reserve_ram_top(gd->bd->bi_dram[0].size)) { 768 gd->arch.resv_ram = gd->bd->bi_dram[0].start + 769 gd->bd->bi_dram[0].size - 770 board_reserve_ram_top(gd->bd->bi_dram[0].size); 771 } 772 } 773 #endif /* CONFIG_FSL_MC_ENET */ 774 775 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 776 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 777 #error "This SoC shouldn't have DP DDR" 778 #endif 779 if (soc_has_dp_ddr()) { 780 /* initialize DP-DDR here */ 781 puts("DP-DDR: "); 782 /* 783 * DDR controller use 0 as the base address for binding. 784 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 785 */ 786 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, 787 CONFIG_DP_DDR_CTRL, 788 CONFIG_DP_DDR_NUM_CTRLS, 789 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, 790 NULL, NULL, NULL); 791 if (dp_ddr_size) { 792 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; 793 gd->bd->bi_dram[2].size = dp_ddr_size; 794 } else { 795 puts("Not detected"); 796 } 797 } 798 #endif 799 800 return 0; 801 } 802 803 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) 804 void efi_add_known_memory(void) 805 { 806 int i; 807 phys_addr_t ram_start, start; 808 phys_size_t ram_size; 809 u64 pages; 810 811 /* Add RAM */ 812 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 813 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 814 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 815 #error "This SoC shouldn't have DP DDR" 816 #endif 817 if (i == 2) 818 continue; /* skip DP-DDR */ 819 #endif 820 ram_start = gd->bd->bi_dram[i].start; 821 ram_size = gd->bd->bi_dram[i].size; 822 #ifdef CONFIG_RESV_RAM 823 if (gd->arch.resv_ram >= ram_start && 824 gd->arch.resv_ram < ram_start + ram_size) 825 ram_size = gd->arch.resv_ram - ram_start; 826 #endif 827 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; 828 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; 829 830 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, 831 false); 832 } 833 } 834 #endif 835 836 /* 837 * Before DDR size is known, early MMU table have DDR mapped as device memory 838 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" 839 * needs to be set for these mappings. 840 * If a special case configures DDR with holes in the mapping, the holes need 841 * to be marked as invalid. This is not implemented in this function. 842 */ 843 void update_early_mmu_table(void) 844 { 845 if (!gd->arch.tlb_addr) 846 return; 847 848 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { 849 mmu_change_region_attr( 850 CONFIG_SYS_SDRAM_BASE, 851 gd->ram_size, 852 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 853 PTE_BLOCK_OUTER_SHARE | 854 PTE_BLOCK_NS | 855 PTE_TYPE_VALID); 856 } else { 857 mmu_change_region_attr( 858 CONFIG_SYS_SDRAM_BASE, 859 CONFIG_SYS_DDR_BLOCK1_SIZE, 860 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 861 PTE_BLOCK_OUTER_SHARE | 862 PTE_BLOCK_NS | 863 PTE_TYPE_VALID); 864 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 865 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE 866 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" 867 #endif 868 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > 869 CONFIG_SYS_DDR_BLOCK2_SIZE) { 870 mmu_change_region_attr( 871 CONFIG_SYS_DDR_BLOCK2_BASE, 872 CONFIG_SYS_DDR_BLOCK2_SIZE, 873 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 874 PTE_BLOCK_OUTER_SHARE | 875 PTE_BLOCK_NS | 876 PTE_TYPE_VALID); 877 mmu_change_region_attr( 878 CONFIG_SYS_DDR_BLOCK3_BASE, 879 gd->ram_size - 880 CONFIG_SYS_DDR_BLOCK1_SIZE - 881 CONFIG_SYS_DDR_BLOCK2_SIZE, 882 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 883 PTE_BLOCK_OUTER_SHARE | 884 PTE_BLOCK_NS | 885 PTE_TYPE_VALID); 886 } else 887 #endif 888 { 889 mmu_change_region_attr( 890 CONFIG_SYS_DDR_BLOCK2_BASE, 891 gd->ram_size - 892 CONFIG_SYS_DDR_BLOCK1_SIZE, 893 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 894 PTE_BLOCK_OUTER_SHARE | 895 PTE_BLOCK_NS | 896 PTE_TYPE_VALID); 897 } 898 } 899 } 900 901 __weak int dram_init(void) 902 { 903 fsl_initdram(); 904 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 905 /* This will break-before-make MMU for DDR */ 906 update_early_mmu_table(); 907 #endif 908 909 return 0; 910 } 911