1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <fsl_ddr_sdram.h> 10 #include <asm/io.h> 11 #include <linux/errno.h> 12 #include <asm/system.h> 13 #include <asm/armv8/mmu.h> 14 #include <asm/io.h> 15 #include <asm/arch/fsl_serdes.h> 16 #include <asm/arch/soc.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/speed.h> 19 #include <asm/arch/mp.h> 20 #include <efi_loader.h> 21 #include <fm_eth.h> 22 #include <fsl-mc/fsl_mc.h> 23 #ifdef CONFIG_FSL_ESDHC 24 #include <fsl_esdhc.h> 25 #endif 26 #include <asm/armv8/sec_firmware.h> 27 #ifdef CONFIG_SYS_FSL_DDR 28 #include <fsl_ddr.h> 29 #endif 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 struct mm_region *mem_map = early_map; 34 35 void cpu_name(char *name) 36 { 37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 38 unsigned int i, svr, ver; 39 40 svr = gur_in32(&gur->svr); 41 ver = SVR_SOC_VER(svr); 42 43 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 44 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { 45 strcpy(name, cpu_type_list[i].name); 46 47 if (IS_E_PROCESSOR(svr)) 48 strcat(name, "E"); 49 50 sprintf(name + strlen(name), " Rev%d.%d", 51 SVR_MAJ(svr), SVR_MIN(svr)); 52 break; 53 } 54 55 if (i == ARRAY_SIZE(cpu_type_list)) 56 strcpy(name, "unknown"); 57 } 58 59 #ifndef CONFIG_SYS_DCACHE_OFF 60 /* 61 * To start MMU before DDR is available, we create MMU table in SRAM. 62 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three 63 * levels of translation tables here to cover 40-bit address space. 64 * We use 4KB granule size, with 40 bits physical address, T0SZ=24 65 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. 66 * Note, the debug print in cache_v8.c is not usable for debugging 67 * these early MMU tables because UART is not yet available. 68 */ 69 static inline void early_mmu_setup(void) 70 { 71 unsigned int el = current_el(); 72 73 /* global data is already setup, no allocation yet */ 74 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; 75 gd->arch.tlb_fillptr = gd->arch.tlb_addr; 76 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; 77 78 /* Create early page tables */ 79 setup_pgtables(); 80 81 /* point TTBR to the new table */ 82 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, 83 get_tcr(el, NULL, NULL) & 84 ~(TCR_ORGN_MASK | TCR_IRGN_MASK), 85 MEMORY_ATTRIBUTES); 86 87 set_sctlr(get_sctlr() | CR_M); 88 } 89 90 static void fix_pcie_mmu_map(void) 91 { 92 #ifdef CONFIG_ARCH_LS2080A 93 unsigned int i; 94 u32 svr, ver; 95 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 96 97 svr = gur_in32(&gur->svr); 98 ver = SVR_SOC_VER(svr); 99 100 /* Fix PCIE base and size for LS2088A */ 101 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || 102 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || 103 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { 104 for (i = 0; i < ARRAY_SIZE(final_map); i++) { 105 switch (final_map[i].phys) { 106 case CONFIG_SYS_PCIE1_PHYS_ADDR: 107 final_map[i].phys = 0x2000000000ULL; 108 final_map[i].virt = 0x2000000000ULL; 109 final_map[i].size = 0x800000000ULL; 110 break; 111 case CONFIG_SYS_PCIE2_PHYS_ADDR: 112 final_map[i].phys = 0x2800000000ULL; 113 final_map[i].virt = 0x2800000000ULL; 114 final_map[i].size = 0x800000000ULL; 115 break; 116 case CONFIG_SYS_PCIE3_PHYS_ADDR: 117 final_map[i].phys = 0x3000000000ULL; 118 final_map[i].virt = 0x3000000000ULL; 119 final_map[i].size = 0x800000000ULL; 120 break; 121 case CONFIG_SYS_PCIE4_PHYS_ADDR: 122 final_map[i].phys = 0x3800000000ULL; 123 final_map[i].virt = 0x3800000000ULL; 124 final_map[i].size = 0x800000000ULL; 125 break; 126 default: 127 break; 128 } 129 } 130 } 131 #endif 132 } 133 134 /* 135 * The final tables look similar to early tables, but different in detail. 136 * These tables are in DRAM. Sub tables are added to enable cache for 137 * QBMan and OCRAM. 138 * 139 * Put the MMU table in secure memory if gd->arch.secure_ram is valid. 140 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. 141 */ 142 static inline void final_mmu_setup(void) 143 { 144 u64 tlb_addr_save = gd->arch.tlb_addr; 145 unsigned int el = current_el(); 146 int index; 147 148 /* fix the final_map before filling in the block entries */ 149 fix_pcie_mmu_map(); 150 151 mem_map = final_map; 152 153 /* Update mapping for DDR to actual size */ 154 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { 155 /* 156 * Find the entry for DDR mapping and update the address and 157 * size. Zero-sized mapping will be skipped when creating MMU 158 * table. 159 */ 160 switch (final_map[index].virt) { 161 case CONFIG_SYS_FSL_DRAM_BASE1: 162 final_map[index].virt = gd->bd->bi_dram[0].start; 163 final_map[index].phys = gd->bd->bi_dram[0].start; 164 final_map[index].size = gd->bd->bi_dram[0].size; 165 break; 166 #ifdef CONFIG_SYS_FSL_DRAM_BASE2 167 case CONFIG_SYS_FSL_DRAM_BASE2: 168 #if (CONFIG_NR_DRAM_BANKS >= 2) 169 final_map[index].virt = gd->bd->bi_dram[1].start; 170 final_map[index].phys = gd->bd->bi_dram[1].start; 171 final_map[index].size = gd->bd->bi_dram[1].size; 172 #else 173 final_map[index].size = 0; 174 #endif 175 break; 176 #endif 177 #ifdef CONFIG_SYS_FSL_DRAM_BASE3 178 case CONFIG_SYS_FSL_DRAM_BASE3: 179 #if (CONFIG_NR_DRAM_BANKS >= 3) 180 final_map[index].virt = gd->bd->bi_dram[2].start; 181 final_map[index].phys = gd->bd->bi_dram[2].start; 182 final_map[index].size = gd->bd->bi_dram[2].size; 183 #else 184 final_map[index].size = 0; 185 #endif 186 break; 187 #endif 188 default: 189 break; 190 } 191 } 192 193 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 194 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { 195 if (el == 3) { 196 /* 197 * Only use gd->arch.secure_ram if the address is 198 * recalculated. Align to 4KB for MMU table. 199 */ 200 /* put page tables in secure ram */ 201 index = ARRAY_SIZE(final_map) - 2; 202 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; 203 final_map[index].virt = gd->arch.secure_ram & ~0x3; 204 final_map[index].phys = final_map[index].virt; 205 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; 206 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; 207 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; 208 tlb_addr_save = gd->arch.tlb_addr; 209 } else { 210 /* Use allocated (board_f.c) memory for TLB */ 211 tlb_addr_save = gd->arch.tlb_allocated; 212 gd->arch.tlb_addr = tlb_addr_save; 213 } 214 } 215 #endif 216 217 /* Reset the fill ptr */ 218 gd->arch.tlb_fillptr = tlb_addr_save; 219 220 /* Create normal system page tables */ 221 setup_pgtables(); 222 223 /* Create emergency page tables */ 224 gd->arch.tlb_addr = gd->arch.tlb_fillptr; 225 gd->arch.tlb_emerg = gd->arch.tlb_addr; 226 setup_pgtables(); 227 gd->arch.tlb_addr = tlb_addr_save; 228 229 /* Disable cache and MMU */ 230 dcache_disable(); /* TLBs are invalidated */ 231 invalidate_icache_all(); 232 233 /* point TTBR to the new table */ 234 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), 235 MEMORY_ATTRIBUTES); 236 237 set_sctlr(get_sctlr() | CR_M); 238 } 239 240 u64 get_page_table_size(void) 241 { 242 return 0x10000; 243 } 244 245 int arch_cpu_init(void) 246 { 247 icache_enable(); 248 __asm_invalidate_dcache_all(); 249 __asm_invalidate_tlb_all(); 250 early_mmu_setup(); 251 set_sctlr(get_sctlr() | CR_C); 252 return 0; 253 } 254 255 void mmu_setup(void) 256 { 257 final_mmu_setup(); 258 } 259 260 /* 261 * This function is called from common/board_r.c. 262 * It recreates MMU table in main memory. 263 */ 264 void enable_caches(void) 265 { 266 mmu_setup(); 267 __asm_invalidate_tlb_all(); 268 icache_enable(); 269 dcache_enable(); 270 } 271 #endif 272 273 u32 initiator_type(u32 cluster, int init_id) 274 { 275 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 276 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 277 u32 type = 0; 278 279 type = gur_in32(&gur->tp_ityp[idx]); 280 if (type & TP_ITYP_AV) 281 return type; 282 283 return 0; 284 } 285 286 u32 cpu_pos_mask(void) 287 { 288 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 289 int i = 0; 290 u32 cluster, type, mask = 0; 291 292 do { 293 int j; 294 295 cluster = gur_in32(&gur->tp_cluster[i].lower); 296 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 297 type = initiator_type(cluster, j); 298 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) 299 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); 300 } 301 i++; 302 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 303 304 return mask; 305 } 306 307 u32 cpu_mask(void) 308 { 309 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 310 int i = 0, count = 0; 311 u32 cluster, type, mask = 0; 312 313 do { 314 int j; 315 316 cluster = gur_in32(&gur->tp_cluster[i].lower); 317 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 318 type = initiator_type(cluster, j); 319 if (type) { 320 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) 321 mask |= 1 << count; 322 count++; 323 } 324 } 325 i++; 326 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 327 328 return mask; 329 } 330 331 /* 332 * Return the number of cores on this SOC. 333 */ 334 int cpu_numcores(void) 335 { 336 return hweight32(cpu_mask()); 337 } 338 339 int fsl_qoriq_core_to_cluster(unsigned int core) 340 { 341 struct ccsr_gur __iomem *gur = 342 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 343 int i = 0, count = 0; 344 u32 cluster; 345 346 do { 347 int j; 348 349 cluster = gur_in32(&gur->tp_cluster[i].lower); 350 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 351 if (initiator_type(cluster, j)) { 352 if (count == core) 353 return i; 354 count++; 355 } 356 } 357 i++; 358 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 359 360 return -1; /* cannot identify the cluster */ 361 } 362 363 u32 fsl_qoriq_core_to_type(unsigned int core) 364 { 365 struct ccsr_gur __iomem *gur = 366 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); 367 int i = 0, count = 0; 368 u32 cluster, type; 369 370 do { 371 int j; 372 373 cluster = gur_in32(&gur->tp_cluster[i].lower); 374 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 375 type = initiator_type(cluster, j); 376 if (type) { 377 if (count == core) 378 return type; 379 count++; 380 } 381 } 382 i++; 383 } while ((cluster & TP_CLUSTER_EOC) == 0x0); 384 385 return -1; /* cannot identify the cluster */ 386 } 387 388 #ifndef CONFIG_FSL_LSCH3 389 uint get_svr(void) 390 { 391 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 392 393 return gur_in32(&gur->svr); 394 } 395 #endif 396 397 #ifdef CONFIG_DISPLAY_CPUINFO 398 int print_cpuinfo(void) 399 { 400 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 401 struct sys_info sysinfo; 402 char buf[32]; 403 unsigned int i, core; 404 u32 type, rcw, svr = gur_in32(&gur->svr); 405 406 puts("SoC: "); 407 408 cpu_name(buf); 409 printf(" %s (0x%x)\n", buf, svr); 410 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 411 get_sys_info(&sysinfo); 412 puts("Clock Configuration:"); 413 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { 414 if (!(i % 3)) 415 puts("\n "); 416 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); 417 printf("CPU%d(%s):%-4s MHz ", core, 418 type == TY_ITYP_VER_A7 ? "A7 " : 419 (type == TY_ITYP_VER_A53 ? "A53" : 420 (type == TY_ITYP_VER_A57 ? "A57" : 421 (type == TY_ITYP_VER_A72 ? "A72" : " "))), 422 strmhz(buf, sysinfo.freq_processor[core])); 423 } 424 /* Display platform clock as Bus frequency. */ 425 printf("\n Bus: %-4s MHz ", 426 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); 427 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); 428 #ifdef CONFIG_SYS_DPAA_FMAN 429 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); 430 #endif 431 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 432 if (soc_has_dp_ddr()) { 433 printf(" DP-DDR: %-4s MT/s", 434 strmhz(buf, sysinfo.freq_ddrbus2)); 435 } 436 #endif 437 puts("\n"); 438 439 /* 440 * Display the RCW, so that no one gets confused as to what RCW 441 * we're actually using for this boot. 442 */ 443 puts("Reset Configuration Word (RCW):"); 444 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 445 rcw = gur_in32(&gur->rcwsr[i]); 446 if ((i % 4) == 0) 447 printf("\n %08x:", i * 4); 448 printf(" %08x", rcw); 449 } 450 puts("\n"); 451 452 return 0; 453 } 454 #endif 455 456 #ifdef CONFIG_FSL_ESDHC 457 int cpu_mmc_init(bd_t *bis) 458 { 459 return fsl_esdhc_mmc_init(bis); 460 } 461 #endif 462 463 int cpu_eth_init(bd_t *bis) 464 { 465 int error = 0; 466 467 #ifdef CONFIG_FSL_MC_ENET 468 error = fsl_mc_ldpaa_init(bis); 469 #endif 470 #ifdef CONFIG_FMAN_ENET 471 fm_standard_init(bis); 472 #endif 473 return error; 474 } 475 476 static inline int check_psci(void) 477 { 478 unsigned int psci_ver; 479 480 psci_ver = sec_firmware_support_psci_version(); 481 if (psci_ver == PSCI_INVALID_VER) 482 return 1; 483 484 return 0; 485 } 486 487 int arch_early_init_r(void) 488 { 489 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 490 u32 svr_dev_id; 491 /* 492 * erratum A009635 is valid only for LS2080A SoC and 493 * its personalitiesi 494 */ 495 svr_dev_id = get_svr() >> 16; 496 if (svr_dev_id == SVR_DEV_LS2080A) 497 erratum_a009635(); 498 #endif 499 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) 500 erratum_a009942_check_cpo(); 501 #endif 502 if (check_psci()) { 503 debug("PSCI: PSCI does not exist.\n"); 504 505 /* if PSCI does not exist, boot secondary cores here */ 506 if (fsl_layerscape_wake_seconday_cores()) 507 printf("Did not wake secondary cores\n"); 508 } 509 510 #ifdef CONFIG_SYS_HAS_SERDES 511 fsl_serdes_init(); 512 #endif 513 #ifdef CONFIG_FMAN_ENET 514 fman_enet_init(); 515 #endif 516 return 0; 517 } 518 519 int timer_init(void) 520 { 521 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; 522 #ifdef CONFIG_FSL_LSCH3 523 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; 524 #endif 525 #ifdef CONFIG_ARCH_LS2080A 526 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; 527 u32 svr_dev_id; 528 #endif 529 #ifdef COUNTER_FREQUENCY_REAL 530 unsigned long cntfrq = COUNTER_FREQUENCY_REAL; 531 532 /* Update with accurate clock frequency */ 533 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); 534 #endif 535 536 #ifdef CONFIG_FSL_LSCH3 537 /* Enable timebase for all clusters. 538 * It is safe to do so even some clusters are not enabled. 539 */ 540 out_le32(cltbenr, 0xf); 541 #endif 542 543 #ifdef CONFIG_ARCH_LS2080A 544 /* 545 * In certain Layerscape SoCs, the clock for each core's 546 * has an enable bit in the PMU Physical Core Time Base Enable 547 * Register (PCTBENR), which allows the watchdog to operate. 548 */ 549 setbits_le32(pctbenr, 0xff); 550 /* 551 * For LS2080A SoC and its personalities, timer controller 552 * offset is different 553 */ 554 svr_dev_id = get_svr() >> 16; 555 if (svr_dev_id == SVR_DEV_LS2080A) 556 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; 557 558 #endif 559 560 /* Enable clock for timer 561 * This is a global setting. 562 */ 563 out_le32(cntcr, 0x1); 564 565 return 0; 566 } 567 568 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; 569 570 void __efi_runtime reset_cpu(ulong addr) 571 { 572 u32 val; 573 574 /* Raise RESET_REQ_B */ 575 val = scfg_in32(rstcr); 576 val |= 0x02; 577 scfg_out32(rstcr, val); 578 } 579 580 #ifdef CONFIG_EFI_LOADER 581 582 void __efi_runtime EFIAPI efi_reset_system( 583 enum efi_reset_type reset_type, 584 efi_status_t reset_status, 585 unsigned long data_size, void *reset_data) 586 { 587 switch (reset_type) { 588 case EFI_RESET_COLD: 589 case EFI_RESET_WARM: 590 reset_cpu(0); 591 break; 592 case EFI_RESET_SHUTDOWN: 593 /* Nothing we can do */ 594 break; 595 } 596 597 while (1) { } 598 } 599 600 void efi_reset_system_init(void) 601 { 602 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); 603 } 604 605 #endif 606 607 phys_size_t board_reserve_ram_top(phys_size_t ram_size) 608 { 609 phys_size_t ram_top = ram_size; 610 611 #ifdef CONFIG_FSL_MC_ENET 612 /* The start address of MC reserved memory needs to be aligned. */ 613 ram_top -= mc_get_dram_block_size(); 614 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); 615 #endif 616 617 return ram_size - ram_top; 618 } 619 620 phys_size_t get_effective_memsize(void) 621 { 622 phys_size_t ea_size, rem = 0; 623 624 /* 625 * For ARMv8 SoCs, DDR memory is split into two or three regions. The 626 * first region is 2GB space at 0x8000_0000. If the memory extends to 627 * the second region (or the third region if applicable), the secure 628 * memory and Management Complex (MC) memory should be put into the 629 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED 630 * is set to the size of first region so U-Boot doesn't relocate itself 631 * into higher address. Should DDR be configured to skip the first 632 * region, this function needs to be adjusted. 633 */ 634 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 635 ea_size = CONFIG_MAX_MEM_MAPPED; 636 rem = gd->ram_size - ea_size; 637 } else { 638 ea_size = gd->ram_size; 639 } 640 641 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 642 /* Check if we have enough space for secure memory */ 643 if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { 644 rem -= CONFIG_SYS_MEM_RESERVE_SECURE; 645 } else { 646 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { 647 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 648 rem = 0; /* Presume MC requires more memory */ 649 } else { 650 printf("Error: No enough space for secure memory.\n"); 651 } 652 } 653 #endif 654 /* Check if we have enough memory for MC */ 655 if (rem < board_reserve_ram_top(rem)) { 656 /* Not enough memory in high region to reserve */ 657 if (ea_size > board_reserve_ram_top(rem)) 658 ea_size -= board_reserve_ram_top(rem); 659 else 660 printf("Error: No enough space for reserved memory.\n"); 661 } 662 663 return ea_size; 664 } 665 666 int dram_init_banksize(void) 667 { 668 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 669 phys_size_t dp_ddr_size; 670 #endif 671 672 /* 673 * gd->ram_size has the total size of DDR memory, less reserved secure 674 * memory. The DDR extends from low region to high region(s) presuming 675 * no hole is created with DDR configuration. gd->arch.secure_ram tracks 676 * the location of secure memory. gd->arch.resv_ram tracks the location 677 * of reserved memory for Management Complex (MC). 678 */ 679 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 680 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { 681 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; 682 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 683 gd->bd->bi_dram[1].size = gd->ram_size - 684 CONFIG_SYS_DDR_BLOCK1_SIZE; 685 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 686 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { 687 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; 688 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - 689 CONFIG_SYS_DDR_BLOCK2_SIZE; 690 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; 691 } 692 #endif 693 } else { 694 gd->bd->bi_dram[0].size = gd->ram_size; 695 } 696 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 697 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 698 if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 699 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; 700 gd->arch.secure_ram = gd->bd->bi_dram[2].start + 701 gd->bd->bi_dram[2].size; 702 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 703 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 704 } else 705 #endif 706 { 707 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { 708 gd->bd->bi_dram[1].size -= 709 CONFIG_SYS_MEM_RESERVE_SECURE; 710 gd->arch.secure_ram = gd->bd->bi_dram[1].start + 711 gd->bd->bi_dram[1].size; 712 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 713 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 714 } else if (gd->bd->bi_dram[0].size > 715 CONFIG_SYS_MEM_RESERVE_SECURE) { 716 gd->bd->bi_dram[0].size -= 717 CONFIG_SYS_MEM_RESERVE_SECURE; 718 gd->arch.secure_ram = gd->bd->bi_dram[0].start + 719 gd->bd->bi_dram[0].size; 720 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 721 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; 722 } 723 } 724 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ 725 726 #ifdef CONFIG_FSL_MC_ENET 727 /* Assign memory for MC */ 728 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 729 if (gd->bd->bi_dram[2].size >= 730 board_reserve_ram_top(gd->bd->bi_dram[2].size)) { 731 gd->arch.resv_ram = gd->bd->bi_dram[2].start + 732 gd->bd->bi_dram[2].size - 733 board_reserve_ram_top(gd->bd->bi_dram[2].size); 734 } else 735 #endif 736 { 737 if (gd->bd->bi_dram[1].size >= 738 board_reserve_ram_top(gd->bd->bi_dram[1].size)) { 739 gd->arch.resv_ram = gd->bd->bi_dram[1].start + 740 gd->bd->bi_dram[1].size - 741 board_reserve_ram_top(gd->bd->bi_dram[1].size); 742 } else if (gd->bd->bi_dram[0].size > 743 board_reserve_ram_top(gd->bd->bi_dram[0].size)) { 744 gd->arch.resv_ram = gd->bd->bi_dram[0].start + 745 gd->bd->bi_dram[0].size - 746 board_reserve_ram_top(gd->bd->bi_dram[0].size); 747 } 748 } 749 #endif /* CONFIG_FSL_MC_ENET */ 750 751 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 752 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 753 #error "This SoC shouldn't have DP DDR" 754 #endif 755 if (soc_has_dp_ddr()) { 756 /* initialize DP-DDR here */ 757 puts("DP-DDR: "); 758 /* 759 * DDR controller use 0 as the base address for binding. 760 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 761 */ 762 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, 763 CONFIG_DP_DDR_CTRL, 764 CONFIG_DP_DDR_NUM_CTRLS, 765 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, 766 NULL, NULL, NULL); 767 if (dp_ddr_size) { 768 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; 769 gd->bd->bi_dram[2].size = dp_ddr_size; 770 } else { 771 puts("Not detected"); 772 } 773 } 774 #endif 775 776 return 0; 777 } 778 779 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) 780 void efi_add_known_memory(void) 781 { 782 int i; 783 phys_addr_t ram_start, start; 784 phys_size_t ram_size; 785 u64 pages; 786 787 /* Add RAM */ 788 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 789 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 790 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 791 #error "This SoC shouldn't have DP DDR" 792 #endif 793 if (i == 2) 794 continue; /* skip DP-DDR */ 795 #endif 796 ram_start = gd->bd->bi_dram[i].start; 797 ram_size = gd->bd->bi_dram[i].size; 798 #ifdef CONFIG_RESV_RAM 799 if (gd->arch.resv_ram >= ram_start && 800 gd->arch.resv_ram < ram_start + ram_size) 801 ram_size = gd->arch.resv_ram - ram_start; 802 #endif 803 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; 804 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; 805 806 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, 807 false); 808 } 809 } 810 #endif 811 812 /* 813 * Before DDR size is known, early MMU table have DDR mapped as device memory 814 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" 815 * needs to be set for these mappings. 816 * If a special case configures DDR with holes in the mapping, the holes need 817 * to be marked as invalid. This is not implemented in this function. 818 */ 819 void update_early_mmu_table(void) 820 { 821 if (!gd->arch.tlb_addr) 822 return; 823 824 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { 825 mmu_change_region_attr( 826 CONFIG_SYS_SDRAM_BASE, 827 gd->ram_size, 828 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 829 PTE_BLOCK_OUTER_SHARE | 830 PTE_BLOCK_NS | 831 PTE_TYPE_VALID); 832 } else { 833 mmu_change_region_attr( 834 CONFIG_SYS_SDRAM_BASE, 835 CONFIG_SYS_DDR_BLOCK1_SIZE, 836 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 837 PTE_BLOCK_OUTER_SHARE | 838 PTE_BLOCK_NS | 839 PTE_TYPE_VALID); 840 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE 841 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE 842 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" 843 #endif 844 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > 845 CONFIG_SYS_DDR_BLOCK2_SIZE) { 846 mmu_change_region_attr( 847 CONFIG_SYS_DDR_BLOCK2_BASE, 848 CONFIG_SYS_DDR_BLOCK2_SIZE, 849 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 850 PTE_BLOCK_OUTER_SHARE | 851 PTE_BLOCK_NS | 852 PTE_TYPE_VALID); 853 mmu_change_region_attr( 854 CONFIG_SYS_DDR_BLOCK3_BASE, 855 gd->ram_size - 856 CONFIG_SYS_DDR_BLOCK1_SIZE - 857 CONFIG_SYS_DDR_BLOCK2_SIZE, 858 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 859 PTE_BLOCK_OUTER_SHARE | 860 PTE_BLOCK_NS | 861 PTE_TYPE_VALID); 862 } else 863 #endif 864 { 865 mmu_change_region_attr( 866 CONFIG_SYS_DDR_BLOCK2_BASE, 867 gd->ram_size - 868 CONFIG_SYS_DDR_BLOCK1_SIZE, 869 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 870 PTE_BLOCK_OUTER_SHARE | 871 PTE_BLOCK_NS | 872 PTE_TYPE_VALID); 873 } 874 } 875 } 876 877 __weak int dram_init(void) 878 { 879 fsl_initdram(); 880 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 881 /* This will break-before-make MMU for DDR */ 882 update_early_mmu_table(); 883 #endif 884 885 return 0; 886 } 887