1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 5 select FSL_LSCH2 6 select SYS_FSL_SRDS_1 7 select SYS_HAS_SERDES 8 select SYS_FSL_DDR_BE 9 select SYS_FSL_MMDC 10 select SYS_FSL_ERRATUM_A010315 11 select SYS_FSL_ERRATUM_A009798 12 select SYS_FSL_ERRATUM_A008997 13 select SYS_FSL_ERRATUM_A009007 14 select SYS_FSL_ERRATUM_A009008 15 select ARCH_EARLY_INIT_R 16 select BOARD_EARLY_INIT_F 17 select SYS_I2C_MXC 18 select SYS_I2C_MXC_I2C1 19 select SYS_I2C_MXC_I2C2 20 imply PANIC_HANG 21 22config ARCH_LS1043A 23 bool 24 select ARMV8_SET_SMPEN 25 select ARM_ERRATA_855873 26 select FSL_LSCH2 27 select SYS_FSL_SRDS_1 28 select SYS_HAS_SERDES 29 select SYS_FSL_DDR 30 select SYS_FSL_DDR_BE 31 select SYS_FSL_DDR_VER_50 32 select SYS_FSL_ERRATUM_A008850 33 select SYS_FSL_ERRATUM_A008997 34 select SYS_FSL_ERRATUM_A009007 35 select SYS_FSL_ERRATUM_A009008 36 select SYS_FSL_ERRATUM_A009660 37 select SYS_FSL_ERRATUM_A009663 38 select SYS_FSL_ERRATUM_A009798 39 select SYS_FSL_ERRATUM_A009929 40 select SYS_FSL_ERRATUM_A009942 41 select SYS_FSL_ERRATUM_A010315 42 select SYS_FSL_ERRATUM_A010539 43 select SYS_FSL_HAS_DDR3 44 select SYS_FSL_HAS_DDR4 45 select ARCH_EARLY_INIT_R 46 select BOARD_EARLY_INIT_F 47 select SYS_I2C_MXC 48 select SYS_I2C_MXC_I2C1 49 select SYS_I2C_MXC_I2C2 50 select SYS_I2C_MXC_I2C3 51 select SYS_I2C_MXC_I2C4 52 imply SCSI 53 imply SCSI_AHCI 54 imply CMD_PCI 55 56config ARCH_LS1046A 57 bool 58 select ARMV8_SET_SMPEN 59 select FSL_LSCH2 60 select SYS_FSL_SRDS_1 61 select SYS_HAS_SERDES 62 select SYS_FSL_DDR 63 select SYS_FSL_DDR_BE 64 select SYS_FSL_DDR_VER_50 65 select SYS_FSL_ERRATUM_A008336 66 select SYS_FSL_ERRATUM_A008511 67 select SYS_FSL_ERRATUM_A008850 68 select SYS_FSL_ERRATUM_A008997 69 select SYS_FSL_ERRATUM_A009007 70 select SYS_FSL_ERRATUM_A009008 71 select SYS_FSL_ERRATUM_A009798 72 select SYS_FSL_ERRATUM_A009801 73 select SYS_FSL_ERRATUM_A009803 74 select SYS_FSL_ERRATUM_A009942 75 select SYS_FSL_ERRATUM_A010165 76 select SYS_FSL_ERRATUM_A010539 77 select SYS_FSL_HAS_DDR4 78 select SYS_FSL_SRDS_2 79 select ARCH_EARLY_INIT_R 80 select BOARD_EARLY_INIT_F 81 select SYS_I2C_MXC 82 select SYS_I2C_MXC_I2C1 83 select SYS_I2C_MXC_I2C2 84 select SYS_I2C_MXC_I2C3 85 select SYS_I2C_MXC_I2C4 86 imply SCSI 87 imply SCSI_AHCI 88 89config ARCH_LS1088A 90 bool 91 select ARMV8_SET_SMPEN 92 select ARM_ERRATA_855873 93 select FSL_LSCH3 94 select SYS_FSL_SRDS_1 95 select SYS_HAS_SERDES 96 select SYS_FSL_DDR 97 select SYS_FSL_DDR_LE 98 select SYS_FSL_DDR_VER_50 99 select SYS_FSL_EC1 100 select SYS_FSL_EC2 101 select SYS_FSL_ERRATUM_A009803 102 select SYS_FSL_ERRATUM_A009942 103 select SYS_FSL_ERRATUM_A010165 104 select SYS_FSL_ERRATUM_A008511 105 select SYS_FSL_ERRATUM_A008850 106 select SYS_FSL_ERRATUM_A009007 107 select SYS_FSL_HAS_CCI400 108 select SYS_FSL_HAS_DDR4 109 select SYS_FSL_HAS_RGMII 110 select SYS_FSL_HAS_SEC 111 select SYS_FSL_SEC_COMPAT_5 112 select SYS_FSL_SEC_LE 113 select SYS_FSL_SRDS_1 114 select SYS_FSL_SRDS_2 115 select FSL_TZASC_1 116 select ARCH_EARLY_INIT_R 117 select BOARD_EARLY_INIT_F 118 select SYS_I2C_MXC 119 select SYS_I2C_MXC_I2C1 120 select SYS_I2C_MXC_I2C2 121 select SYS_I2C_MXC_I2C3 122 select SYS_I2C_MXC_I2C4 123 imply SCSI 124 imply PANIC_HANG 125 126config ARCH_LS2080A 127 bool 128 select ARMV8_SET_SMPEN 129 select ARM_ERRATA_826974 130 select ARM_ERRATA_828024 131 select ARM_ERRATA_829520 132 select ARM_ERRATA_833471 133 select FSL_LSCH3 134 select SYS_FSL_SRDS_1 135 select SYS_HAS_SERDES 136 select SYS_FSL_DDR 137 select SYS_FSL_DDR_LE 138 select SYS_FSL_DDR_VER_50 139 select SYS_FSL_HAS_CCN504 140 select SYS_FSL_HAS_DP_DDR 141 select SYS_FSL_HAS_SEC 142 select SYS_FSL_HAS_DDR4 143 select SYS_FSL_SEC_COMPAT_5 144 select SYS_FSL_SEC_LE 145 select SYS_FSL_SRDS_2 146 select FSL_TZASC_1 147 select FSL_TZASC_2 148 select SYS_FSL_ERRATUM_A008336 149 select SYS_FSL_ERRATUM_A008511 150 select SYS_FSL_ERRATUM_A008514 151 select SYS_FSL_ERRATUM_A008585 152 select SYS_FSL_ERRATUM_A008997 153 select SYS_FSL_ERRATUM_A009007 154 select SYS_FSL_ERRATUM_A009008 155 select SYS_FSL_ERRATUM_A009635 156 select SYS_FSL_ERRATUM_A009663 157 select SYS_FSL_ERRATUM_A009798 158 select SYS_FSL_ERRATUM_A009801 159 select SYS_FSL_ERRATUM_A009803 160 select SYS_FSL_ERRATUM_A009942 161 select SYS_FSL_ERRATUM_A010165 162 select SYS_FSL_ERRATUM_A009203 163 select ARCH_EARLY_INIT_R 164 select BOARD_EARLY_INIT_F 165 select SYS_I2C_MXC 166 select SYS_I2C_MXC_I2C1 167 select SYS_I2C_MXC_I2C2 168 select SYS_I2C_MXC_I2C3 169 select SYS_I2C_MXC_I2C4 170 imply DISTRO_DEFAULTS 171 imply PANIC_HANG 172 173config FSL_LSCH2 174 bool 175 select SYS_FSL_HAS_CCI400 176 select SYS_FSL_HAS_SEC 177 select SYS_FSL_SEC_COMPAT_5 178 select SYS_FSL_SEC_BE 179 180config FSL_LSCH3 181 bool 182 183config FSL_MC_ENET 184 bool "Management Complex network" 185 depends on ARCH_LS2080A || ARCH_LS1088A 186 default y 187 select RESV_RAM 188 help 189 Enable Management Complex (MC) network 190 191menu "Layerscape architecture" 192 depends on FSL_LSCH2 || FSL_LSCH3 193 194config FSL_PCIE_COMPAT 195 string "PCIe compatible of Kernel DT" 196 depends on PCIE_LAYERSCAPE 197 default "fsl,ls1012a-pcie" if ARCH_LS1012A 198 default "fsl,ls1043a-pcie" if ARCH_LS1043A 199 default "fsl,ls1046a-pcie" if ARCH_LS1046A 200 default "fsl,ls2080a-pcie" if ARCH_LS2080A 201 default "fsl,ls1088a-pcie" if ARCH_LS1088A 202 help 203 This compatible is used to find pci controller node in Kernel DT 204 to complete fixup. 205 206config HAS_FEATURE_GIC64K_ALIGN 207 bool 208 default y if ARCH_LS1043A 209 210config HAS_FEATURE_ENHANCED_MSI 211 bool 212 default y if ARCH_LS1043A 213 214menu "Layerscape PPA" 215config FSL_LS_PPA 216 bool "FSL Layerscape PPA firmware support" 217 depends on !ARMV8_PSCI 218 select ARMV8_SEC_FIRMWARE_SUPPORT 219 select SEC_FIRMWARE_ARMV8_PSCI 220 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 221 help 222 The FSL Primary Protected Application (PPA) is a software component 223 which is loaded during boot stage, and then remains resident in RAM 224 and runs in the TrustZone after boot. 225 Say y to enable it. 226 227config SPL_FSL_LS_PPA 228 bool "FSL Layerscape PPA firmware support for SPL build" 229 depends on !ARMV8_PSCI 230 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 231 select SEC_FIRMWARE_ARMV8_PSCI 232 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 233 help 234 The FSL Primary Protected Application (PPA) is a software component 235 which is loaded during boot stage, and then remains resident in RAM 236 and runs in the TrustZone after boot. This is to load PPA during SPL 237 stage instead of the RAM version of U-Boot. Once PPA is initialized, 238 the rest of U-Boot (including RAM version) runs at EL2. 239choice 240 prompt "FSL Layerscape PPA firmware loading-media select" 241 depends on FSL_LS_PPA 242 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 243 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 244 default SYS_LS_PPA_FW_IN_XIP 245 246config SYS_LS_PPA_FW_IN_XIP 247 bool "XIP" 248 help 249 Say Y here if the PPA firmware locate at XIP flash, such 250 as NOR or QSPI flash. 251 252config SYS_LS_PPA_FW_IN_MMC 253 bool "eMMC or SD Card" 254 help 255 Say Y here if the PPA firmware locate at eMMC/SD card. 256 257config SYS_LS_PPA_FW_IN_NAND 258 bool "NAND" 259 help 260 Say Y here if the PPA firmware locate at NAND flash. 261 262endchoice 263 264config SYS_LS_PPA_FW_ADDR 265 hex "Address of PPA firmware loading from" 266 depends on FSL_LS_PPA 267 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 268 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 269 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 270 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 271 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 272 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 273 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 274 275 help 276 If the PPA firmware locate at XIP flash, such as NOR or 277 QSPI flash, this address is a directly memory-mapped. 278 If it is in a serial accessed flash, such as NAND and SD 279 card, it is a byte offset. 280 281config SYS_LS_PPA_ESBC_ADDR 282 hex "hdr address of PPA firmware loading from" 283 depends on FSL_LS_PPA && CHAIN_OF_TRUST 284 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 285 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 286 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 287 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 288 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 289 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 290 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 291 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 292 help 293 If the PPA header firmware locate at XIP flash, such as NOR or 294 QSPI flash, this address is a directly memory-mapped. 295 If it is in a serial accessed flash, such as NAND and SD 296 card, it is a byte offset. 297 298config LS_PPA_ESBC_HDR_SIZE 299 hex "Length of PPA ESBC header" 300 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 301 default 0x2000 302 help 303 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 304 NAND to memory to validate PPA image. 305 306endmenu 307 308config SYS_FSL_ERRATUM_A008997 309 bool "Workaround for USB PHY erratum A008997" 310 311config SYS_FSL_ERRATUM_A009007 312 bool 313 help 314 Workaround for USB PHY erratum A009007 315 316config SYS_FSL_ERRATUM_A009008 317 bool "Workaround for USB PHY erratum A009008" 318 319config SYS_FSL_ERRATUM_A009798 320 bool "Workaround for USB PHY erratum A009798" 321 322config SYS_FSL_ERRATUM_A010315 323 bool "Workaround for PCIe erratum A010315" 324 325config SYS_FSL_ERRATUM_A010539 326 bool "Workaround for PIN MUX erratum A010539" 327 328config MAX_CPUS 329 int "Maximum number of CPUs permitted for Layerscape" 330 default 4 if ARCH_LS1043A 331 default 4 if ARCH_LS1046A 332 default 16 if ARCH_LS2080A 333 default 8 if ARCH_LS1088A 334 default 1 335 help 336 Set this number to the maximum number of possible CPUs in the SoC. 337 SoCs may have multiple clusters with each cluster may have multiple 338 ports. If some ports are reserved but higher ports are used for 339 cores, count the reserved ports. This will allocate enough memory 340 in spin table to properly handle all cores. 341 342config SECURE_BOOT 343 bool "Secure Boot" 344 help 345 Enable Freescale Secure Boot feature 346 347config QSPI_AHB_INIT 348 bool "Init the QSPI AHB bus" 349 help 350 The default setting for QSPI AHB bus just support 3bytes addressing. 351 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 352 bus for those flashes to support the full QSPI flash size. 353 354config SYS_CCI400_OFFSET 355 hex "Offset for CCI400 base" 356 depends on SYS_FSL_HAS_CCI400 357 default 0x3090000 if ARCH_LS1088A 358 default 0x180000 if FSL_LSCH2 359 help 360 Offset for CCI400 base 361 CCI400 base addr = CCSRBAR + CCI400_OFFSET 362 363config SYS_FSL_IFC_BANK_COUNT 364 int "Maximum banks of Integrated flash controller" 365 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 366 default 4 if ARCH_LS1043A 367 default 4 if ARCH_LS1046A 368 default 8 if ARCH_LS2080A || ARCH_LS1088A 369 370config SYS_FSL_HAS_CCI400 371 bool 372 373config SYS_FSL_HAS_CCN504 374 bool 375 376config SYS_FSL_HAS_DP_DDR 377 bool 378 379config SYS_FSL_SRDS_1 380 bool 381 382config SYS_FSL_SRDS_2 383 bool 384 385config SYS_HAS_SERDES 386 bool 387 388config FSL_TZASC_1 389 bool 390 391config FSL_TZASC_2 392 bool 393 394endmenu 395 396menu "Layerscape clock tree configuration" 397 depends on FSL_LSCH2 || FSL_LSCH3 398 399config SYS_FSL_CLK 400 bool "Enable clock tree initialization" 401 default y 402 403config CLUSTER_CLK_FREQ 404 int "Reference clock of core cluster" 405 depends on ARCH_LS1012A 406 default 100000000 407 help 408 This number is the reference clock frequency of core PLL. 409 For most platforms, the core PLL and Platform PLL have the same 410 reference clock, but for some platforms, LS1012A for instance, 411 they are provided sepatately. 412 413config SYS_FSL_PCLK_DIV 414 int "Platform clock divider" 415 default 1 if ARCH_LS1043A 416 default 1 if ARCH_LS1046A 417 default 1 if ARCH_LS1088A 418 default 2 419 help 420 This is the divider that is used to derive Platform clock from 421 Platform PLL, in another word: 422 Platform_clk = Platform_PLL_freq / this_divider 423 424config SYS_FSL_DSPI_CLK_DIV 425 int "DSPI clock divider" 426 default 1 if ARCH_LS1043A 427 default 2 428 help 429 This is the divider that is used to derive DSPI clock from Platform 430 clock, in another word DSPI_clk = Platform_clk / this_divider. 431 432config SYS_FSL_DUART_CLK_DIV 433 int "DUART clock divider" 434 default 1 if ARCH_LS1043A 435 default 2 436 help 437 This is the divider that is used to derive DUART clock from Platform 438 clock, in another word DUART_clk = Platform_clk / this_divider. 439 440config SYS_FSL_I2C_CLK_DIV 441 int "I2C clock divider" 442 default 1 if ARCH_LS1043A 443 default 2 444 help 445 This is the divider that is used to derive I2C clock from Platform 446 clock, in another word I2C_clk = Platform_clk / this_divider. 447 448config SYS_FSL_IFC_CLK_DIV 449 int "IFC clock divider" 450 default 1 if ARCH_LS1043A 451 default 2 452 help 453 This is the divider that is used to derive IFC clock from Platform 454 clock, in another word IFC_clk = Platform_clk / this_divider. 455 456config SYS_FSL_LPUART_CLK_DIV 457 int "LPUART clock divider" 458 default 1 if ARCH_LS1043A 459 default 2 460 help 461 This is the divider that is used to derive LPUART clock from Platform 462 clock, in another word LPUART_clk = Platform_clk / this_divider. 463 464config SYS_FSL_SDHC_CLK_DIV 465 int "SDHC clock divider" 466 default 1 if ARCH_LS1043A 467 default 1 if ARCH_LS1012A 468 default 2 469 help 470 This is the divider that is used to derive SDHC clock from Platform 471 clock, in another word SDHC_clk = Platform_clk / this_divider. 472endmenu 473 474config RESV_RAM 475 bool 476 help 477 Reserve memory from the top, tracked by gd->arch.resv_ram. This 478 reserved RAM can be used by special driver that resides in memory 479 after U-Boot exits. It's up to implementation to allocate and allow 480 access to this reserved memory. For example, the reserved RAM can 481 be at the high end of physical memory. The reserve RAM may be 482 excluded from memory bank(s) passed to OS, or marked as reserved. 483 484config SYS_FSL_EC1 485 bool 486 help 487 Ethernet controller 1, this is connected to MAC3. 488 Provides DPAA2 capabilities 489 490config SYS_FSL_EC2 491 bool 492 help 493 Ethernet controller 2, this is connected to MAC4. 494 Provides DPAA2 capabilities 495 496config SYS_FSL_ERRATUM_A008336 497 bool 498 499config SYS_FSL_ERRATUM_A008514 500 bool 501 502config SYS_FSL_ERRATUM_A008585 503 bool 504 505config SYS_FSL_ERRATUM_A008850 506 bool 507 508config SYS_FSL_ERRATUM_A009203 509 bool 510 511config SYS_FSL_ERRATUM_A009635 512 bool 513 514config SYS_FSL_ERRATUM_A009660 515 bool 516 517config SYS_FSL_ERRATUM_A009929 518 bool 519 520 521config SYS_FSL_HAS_RGMII 522 bool 523 depends on SYS_FSL_EC1 || SYS_FSL_EC2 524 525 526config SYS_MC_RSV_MEM_ALIGN 527 hex "Management Complex reserved memory alignment" 528 depends on RESV_RAM 529 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A 530 help 531 Reserved memory needs to be aligned for MC to use. Default value 532 is 512MB. 533 534config SPL_LDSCRIPT 535 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 536 537config HAS_FSL_XHCI_USB 538 bool 539 default y if ARCH_LS1043A || ARCH_LS1046A 540 help 541 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 542 pins, select it when the pins are assigned to USB. 543