1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 imply SCSI 30 imply CMD_PCI 31 32config ARCH_LS1046A 33 bool 34 select ARMV8_SET_SMPEN 35 select FSL_LSCH2 36 select SYS_FSL_DDR 37 select SYS_FSL_DDR_BE 38 select SYS_FSL_DDR_VER_50 39 select SYS_FSL_ERRATUM_A008336 40 select SYS_FSL_ERRATUM_A008511 41 select SYS_FSL_ERRATUM_A008850 42 select SYS_FSL_ERRATUM_A009801 43 select SYS_FSL_ERRATUM_A009803 44 select SYS_FSL_ERRATUM_A009942 45 select SYS_FSL_ERRATUM_A010165 46 select SYS_FSL_ERRATUM_A010539 47 select SYS_FSL_HAS_DDR4 48 select SYS_FSL_SRDS_2 49 select ARCH_EARLY_INIT_R 50 select BOARD_EARLY_INIT_F 51 imply SCSI 52 53config ARCH_LS1088A 54 bool 55 select ARMV8_SET_SMPEN 56 select FSL_LSCH3 57 select SYS_FSL_DDR 58 select SYS_FSL_DDR_LE 59 select SYS_FSL_DDR_VER_50 60 select SYS_FSL_ERRATUM_A009803 61 select SYS_FSL_ERRATUM_A009942 62 select SYS_FSL_ERRATUM_A010165 63 select SYS_FSL_ERRATUM_A008511 64 select SYS_FSL_ERRATUM_A008850 65 select SYS_FSL_HAS_CCI400 66 select SYS_FSL_HAS_DDR4 67 select SYS_FSL_HAS_SEC 68 select SYS_FSL_SEC_COMPAT_5 69 select SYS_FSL_SEC_LE 70 select SYS_FSL_SRDS_1 71 select SYS_FSL_SRDS_2 72 select FSL_TZASC_1 73 select ARCH_EARLY_INIT_R 74 select BOARD_EARLY_INIT_F 75 76config ARCH_LS2080A 77 bool 78 select ARMV8_SET_SMPEN 79 select ARM_ERRATA_826974 80 select ARM_ERRATA_828024 81 select ARM_ERRATA_829520 82 select ARM_ERRATA_833471 83 select FSL_LSCH3 84 select SYS_FSL_DDR 85 select SYS_FSL_DDR_LE 86 select SYS_FSL_DDR_VER_50 87 select SYS_FSL_HAS_CCN504 88 select SYS_FSL_HAS_DP_DDR 89 select SYS_FSL_HAS_SEC 90 select SYS_FSL_HAS_DDR4 91 select SYS_FSL_SEC_COMPAT_5 92 select SYS_FSL_SEC_LE 93 select SYS_FSL_SRDS_2 94 select FSL_TZASC_1 95 select FSL_TZASC_2 96 select SYS_FSL_ERRATUM_A008336 97 select SYS_FSL_ERRATUM_A008511 98 select SYS_FSL_ERRATUM_A008514 99 select SYS_FSL_ERRATUM_A008585 100 select SYS_FSL_ERRATUM_A009635 101 select SYS_FSL_ERRATUM_A009663 102 select SYS_FSL_ERRATUM_A009801 103 select SYS_FSL_ERRATUM_A009803 104 select SYS_FSL_ERRATUM_A009942 105 select SYS_FSL_ERRATUM_A010165 106 select SYS_FSL_ERRATUM_A009203 107 select ARCH_EARLY_INIT_R 108 select BOARD_EARLY_INIT_F 109 110config FSL_LSCH2 111 bool 112 select SYS_FSL_HAS_CCI400 113 select SYS_FSL_HAS_SEC 114 select SYS_FSL_SEC_COMPAT_5 115 select SYS_FSL_SEC_BE 116 select SYS_FSL_SRDS_1 117 select SYS_HAS_SERDES 118 119config FSL_LSCH3 120 bool 121 select SYS_FSL_SRDS_1 122 select SYS_HAS_SERDES 123 124config FSL_MC_ENET 125 bool "Management Complex network" 126 depends on ARCH_LS2080A || ARCH_LS1088A 127 default y 128 select RESV_RAM 129 help 130 Enable Management Complex (MC) network 131 132menu "Layerscape architecture" 133 depends on FSL_LSCH2 || FSL_LSCH3 134 135config FSL_PCIE_COMPAT 136 string "PCIe compatible of Kernel DT" 137 depends on PCIE_LAYERSCAPE 138 default "fsl,ls1012a-pcie" if ARCH_LS1012A 139 default "fsl,ls1043a-pcie" if ARCH_LS1043A 140 default "fsl,ls1046a-pcie" if ARCH_LS1046A 141 default "fsl,ls2080a-pcie" if ARCH_LS2080A 142 default "fsl,ls1088a-pcie" if ARCH_LS1088A 143 help 144 This compatible is used to find pci controller node in Kernel DT 145 to complete fixup. 146 147config HAS_FEATURE_GIC64K_ALIGN 148 bool 149 default y if ARCH_LS1043A 150 151config HAS_FEATURE_ENHANCED_MSI 152 bool 153 default y if ARCH_LS1043A 154 155menu "Layerscape PPA" 156config FSL_LS_PPA 157 bool "FSL Layerscape PPA firmware support" 158 depends on !ARMV8_PSCI 159 select ARMV8_SEC_FIRMWARE_SUPPORT 160 select SEC_FIRMWARE_ARMV8_PSCI 161 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 162 help 163 The FSL Primary Protected Application (PPA) is a software component 164 which is loaded during boot stage, and then remains resident in RAM 165 and runs in the TrustZone after boot. 166 Say y to enable it. 167 168config SPL_FSL_LS_PPA 169 bool "FSL Layerscape PPA firmware support for SPL build" 170 depends on !ARMV8_PSCI 171 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 172 select SEC_FIRMWARE_ARMV8_PSCI 173 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 174 help 175 The FSL Primary Protected Application (PPA) is a software component 176 which is loaded during boot stage, and then remains resident in RAM 177 and runs in the TrustZone after boot. This is to load PPA during SPL 178 stage instead of the RAM version of U-Boot. Once PPA is initialized, 179 the rest of U-Boot (including RAM version) runs at EL2. 180choice 181 prompt "FSL Layerscape PPA firmware loading-media select" 182 depends on FSL_LS_PPA 183 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 184 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 185 default SYS_LS_PPA_FW_IN_XIP 186 187config SYS_LS_PPA_FW_IN_XIP 188 bool "XIP" 189 help 190 Say Y here if the PPA firmware locate at XIP flash, such 191 as NOR or QSPI flash. 192 193config SYS_LS_PPA_FW_IN_MMC 194 bool "eMMC or SD Card" 195 help 196 Say Y here if the PPA firmware locate at eMMC/SD card. 197 198config SYS_LS_PPA_FW_IN_NAND 199 bool "NAND" 200 help 201 Say Y here if the PPA firmware locate at NAND flash. 202 203endchoice 204 205config SYS_LS_PPA_FW_ADDR 206 hex "Address of PPA firmware loading from" 207 depends on FSL_LS_PPA 208 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 209 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 210 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 211 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 212 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 213 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 214 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 215 216 help 217 If the PPA firmware locate at XIP flash, such as NOR or 218 QSPI flash, this address is a directly memory-mapped. 219 If it is in a serial accessed flash, such as NAND and SD 220 card, it is a byte offset. 221 222config SYS_LS_PPA_ESBC_ADDR 223 hex "hdr address of PPA firmware loading from" 224 depends on FSL_LS_PPA && CHAIN_OF_TRUST 225 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 226 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 227 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 228 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 229 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 230 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 231 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 232 help 233 If the PPA header firmware locate at XIP flash, such as NOR or 234 QSPI flash, this address is a directly memory-mapped. 235 If it is in a serial accessed flash, such as NAND and SD 236 card, it is a byte offset. 237 238config LS_PPA_ESBC_HDR_SIZE 239 hex "Length of PPA ESBC header" 240 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 241 default 0x2000 242 help 243 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 244 NAND to memory to validate PPA image. 245 246endmenu 247 248config SYS_FSL_ERRATUM_A010315 249 bool "Workaround for PCIe erratum A010315" 250 251config SYS_FSL_ERRATUM_A010539 252 bool "Workaround for PIN MUX erratum A010539" 253 254config MAX_CPUS 255 int "Maximum number of CPUs permitted for Layerscape" 256 default 4 if ARCH_LS1043A 257 default 4 if ARCH_LS1046A 258 default 16 if ARCH_LS2080A 259 default 8 if ARCH_LS1088A 260 default 1 261 help 262 Set this number to the maximum number of possible CPUs in the SoC. 263 SoCs may have multiple clusters with each cluster may have multiple 264 ports. If some ports are reserved but higher ports are used for 265 cores, count the reserved ports. This will allocate enough memory 266 in spin table to properly handle all cores. 267 268config SECURE_BOOT 269 bool "Secure Boot" 270 help 271 Enable Freescale Secure Boot feature 272 273config QSPI_AHB_INIT 274 bool "Init the QSPI AHB bus" 275 help 276 The default setting for QSPI AHB bus just support 3bytes addressing. 277 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 278 bus for those flashes to support the full QSPI flash size. 279 280config SYS_CCI400_OFFSET 281 hex "Offset for CCI400 base" 282 depends on SYS_FSL_HAS_CCI400 283 default 0x3090000 if ARCH_LS1088A 284 default 0x180000 if FSL_LSCH2 285 help 286 Offset for CCI400 base 287 CCI400 base addr = CCSRBAR + CCI400_OFFSET 288 289config SYS_FSL_IFC_BANK_COUNT 290 int "Maximum banks of Integrated flash controller" 291 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 292 default 4 if ARCH_LS1043A 293 default 4 if ARCH_LS1046A 294 default 8 if ARCH_LS2080A || ARCH_LS1088A 295 296config SYS_FSL_HAS_CCI400 297 bool 298 299config SYS_FSL_HAS_CCN504 300 bool 301 302config SYS_FSL_HAS_DP_DDR 303 bool 304 305config SYS_FSL_SRDS_1 306 bool 307 308config SYS_FSL_SRDS_2 309 bool 310 311config SYS_HAS_SERDES 312 bool 313 314config FSL_TZASC_1 315 bool 316 317config FSL_TZASC_2 318 bool 319 320endmenu 321 322menu "Layerscape clock tree configuration" 323 depends on FSL_LSCH2 || FSL_LSCH3 324 325config SYS_FSL_CLK 326 bool "Enable clock tree initialization" 327 default y 328 329config CLUSTER_CLK_FREQ 330 int "Reference clock of core cluster" 331 depends on ARCH_LS1012A 332 default 100000000 333 help 334 This number is the reference clock frequency of core PLL. 335 For most platforms, the core PLL and Platform PLL have the same 336 reference clock, but for some platforms, LS1012A for instance, 337 they are provided sepatately. 338 339config SYS_FSL_PCLK_DIV 340 int "Platform clock divider" 341 default 1 if ARCH_LS1043A 342 default 1 if ARCH_LS1046A 343 default 1 if ARCH_LS1088A 344 default 2 345 help 346 This is the divider that is used to derive Platform clock from 347 Platform PLL, in another word: 348 Platform_clk = Platform_PLL_freq / this_divider 349 350config SYS_FSL_DSPI_CLK_DIV 351 int "DSPI clock divider" 352 default 1 if ARCH_LS1043A 353 default 2 354 help 355 This is the divider that is used to derive DSPI clock from Platform 356 clock, in another word DSPI_clk = Platform_clk / this_divider. 357 358config SYS_FSL_DUART_CLK_DIV 359 int "DUART clock divider" 360 default 1 if ARCH_LS1043A 361 default 2 362 help 363 This is the divider that is used to derive DUART clock from Platform 364 clock, in another word DUART_clk = Platform_clk / this_divider. 365 366config SYS_FSL_I2C_CLK_DIV 367 int "I2C clock divider" 368 default 1 if ARCH_LS1043A 369 default 2 370 help 371 This is the divider that is used to derive I2C clock from Platform 372 clock, in another word I2C_clk = Platform_clk / this_divider. 373 374config SYS_FSL_IFC_CLK_DIV 375 int "IFC clock divider" 376 default 1 if ARCH_LS1043A 377 default 2 378 help 379 This is the divider that is used to derive IFC clock from Platform 380 clock, in another word IFC_clk = Platform_clk / this_divider. 381 382config SYS_FSL_LPUART_CLK_DIV 383 int "LPUART clock divider" 384 default 1 if ARCH_LS1043A 385 default 2 386 help 387 This is the divider that is used to derive LPUART clock from Platform 388 clock, in another word LPUART_clk = Platform_clk / this_divider. 389 390config SYS_FSL_SDHC_CLK_DIV 391 int "SDHC clock divider" 392 default 1 if ARCH_LS1043A 393 default 1 if ARCH_LS1012A 394 default 2 395 help 396 This is the divider that is used to derive SDHC clock from Platform 397 clock, in another word SDHC_clk = Platform_clk / this_divider. 398endmenu 399 400config RESV_RAM 401 bool 402 help 403 Reserve memory from the top, tracked by gd->arch.resv_ram. This 404 reserved RAM can be used by special driver that resides in memory 405 after U-Boot exits. It's up to implementation to allocate and allow 406 access to this reserved memory. For example, the reserved RAM can 407 be at the high end of physical memory. The reserve RAM may be 408 excluded from memory bank(s) passed to OS, or marked as reserved. 409 410config SYS_FSL_ERRATUM_A008336 411 bool 412 413config SYS_FSL_ERRATUM_A008514 414 bool 415 416config SYS_FSL_ERRATUM_A008585 417 bool 418 419config SYS_FSL_ERRATUM_A008850 420 bool 421 422config SYS_FSL_ERRATUM_A009203 423 bool 424 425config SYS_FSL_ERRATUM_A009635 426 bool 427 428config SYS_FSL_ERRATUM_A009660 429 bool 430 431config SYS_FSL_ERRATUM_A009929 432 bool 433 434config SYS_MC_RSV_MEM_ALIGN 435 hex "Management Complex reserved memory alignment" 436 depends on RESV_RAM 437 default 0x20000000 if ARCH_LS2080A 438 default 0x70000000 if ARCH_LS1088A 439 help 440 Reserved memory needs to be aligned for MC to use. Default value 441 is 512MB. 442 443config SPL_LDSCRIPT 444 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 445