1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 5 select FSL_LSCH2 6 select SYS_FSL_DDR_BE 7 select SYS_FSL_MMDC 8 select SYS_FSL_ERRATUM_A010315 9 select SYS_FSL_ERRATUM_A009798 10 select SYS_FSL_ERRATUM_A008997 11 select SYS_FSL_ERRATUM_A009007 12 select SYS_FSL_ERRATUM_A009008 13 select ARCH_EARLY_INIT_R 14 select BOARD_EARLY_INIT_F 15 imply PANIC_HANG 16 17config ARCH_LS1043A 18 bool 19 select ARMV8_SET_SMPEN 20 select ARM_ERRATA_855873 21 select FSL_LSCH2 22 select SYS_FSL_DDR 23 select SYS_FSL_DDR_BE 24 select SYS_FSL_DDR_VER_50 25 select SYS_FSL_ERRATUM_A008850 26 select SYS_FSL_ERRATUM_A008997 27 select SYS_FSL_ERRATUM_A009007 28 select SYS_FSL_ERRATUM_A009008 29 select SYS_FSL_ERRATUM_A009660 30 select SYS_FSL_ERRATUM_A009663 31 select SYS_FSL_ERRATUM_A009798 32 select SYS_FSL_ERRATUM_A009929 33 select SYS_FSL_ERRATUM_A009942 34 select SYS_FSL_ERRATUM_A010315 35 select SYS_FSL_ERRATUM_A010539 36 select SYS_FSL_HAS_DDR3 37 select SYS_FSL_HAS_DDR4 38 select ARCH_EARLY_INIT_R 39 select BOARD_EARLY_INIT_F 40 imply SCSI 41 imply SCSI_AHCI 42 imply CMD_PCI 43 44config ARCH_LS1046A 45 bool 46 select ARMV8_SET_SMPEN 47 select FSL_LSCH2 48 select SYS_FSL_DDR 49 select SYS_FSL_DDR_BE 50 select SYS_FSL_DDR_VER_50 51 select SYS_FSL_ERRATUM_A008336 52 select SYS_FSL_ERRATUM_A008511 53 select SYS_FSL_ERRATUM_A008850 54 select SYS_FSL_ERRATUM_A008997 55 select SYS_FSL_ERRATUM_A009007 56 select SYS_FSL_ERRATUM_A009008 57 select SYS_FSL_ERRATUM_A009798 58 select SYS_FSL_ERRATUM_A009801 59 select SYS_FSL_ERRATUM_A009803 60 select SYS_FSL_ERRATUM_A009942 61 select SYS_FSL_ERRATUM_A010165 62 select SYS_FSL_ERRATUM_A010539 63 select SYS_FSL_HAS_DDR4 64 select SYS_FSL_SRDS_2 65 select ARCH_EARLY_INIT_R 66 select BOARD_EARLY_INIT_F 67 imply SCSI 68 imply SCSI_AHCI 69 70config ARCH_LS1088A 71 bool 72 select ARMV8_SET_SMPEN 73 select ARM_ERRATA_855873 74 select FSL_LSCH3 75 select SYS_FSL_DDR 76 select SYS_FSL_DDR_LE 77 select SYS_FSL_DDR_VER_50 78 select SYS_FSL_EC1 79 select SYS_FSL_EC2 80 select SYS_FSL_ERRATUM_A009803 81 select SYS_FSL_ERRATUM_A009942 82 select SYS_FSL_ERRATUM_A010165 83 select SYS_FSL_ERRATUM_A008511 84 select SYS_FSL_ERRATUM_A008850 85 select SYS_FSL_ERRATUM_A009007 86 select SYS_FSL_HAS_CCI400 87 select SYS_FSL_HAS_DDR4 88 select SYS_FSL_HAS_RGMII 89 select SYS_FSL_HAS_SEC 90 select SYS_FSL_SEC_COMPAT_5 91 select SYS_FSL_SEC_LE 92 select SYS_FSL_SRDS_1 93 select SYS_FSL_SRDS_2 94 select FSL_TZASC_1 95 select ARCH_EARLY_INIT_R 96 select BOARD_EARLY_INIT_F 97 imply SCSI 98 imply PANIC_HANG 99 100config ARCH_LS2080A 101 bool 102 select ARMV8_SET_SMPEN 103 select ARM_ERRATA_826974 104 select ARM_ERRATA_828024 105 select ARM_ERRATA_829520 106 select ARM_ERRATA_833471 107 select FSL_LSCH3 108 select SYS_FSL_DDR 109 select SYS_FSL_DDR_LE 110 select SYS_FSL_DDR_VER_50 111 select SYS_FSL_HAS_CCN504 112 select SYS_FSL_HAS_DP_DDR 113 select SYS_FSL_HAS_SEC 114 select SYS_FSL_HAS_DDR4 115 select SYS_FSL_SEC_COMPAT_5 116 select SYS_FSL_SEC_LE 117 select SYS_FSL_SRDS_2 118 select FSL_TZASC_1 119 select FSL_TZASC_2 120 select SYS_FSL_ERRATUM_A008336 121 select SYS_FSL_ERRATUM_A008511 122 select SYS_FSL_ERRATUM_A008514 123 select SYS_FSL_ERRATUM_A008585 124 select SYS_FSL_ERRATUM_A008997 125 select SYS_FSL_ERRATUM_A009007 126 select SYS_FSL_ERRATUM_A009008 127 select SYS_FSL_ERRATUM_A009635 128 select SYS_FSL_ERRATUM_A009663 129 select SYS_FSL_ERRATUM_A009798 130 select SYS_FSL_ERRATUM_A009801 131 select SYS_FSL_ERRATUM_A009803 132 select SYS_FSL_ERRATUM_A009942 133 select SYS_FSL_ERRATUM_A010165 134 select SYS_FSL_ERRATUM_A009203 135 select ARCH_EARLY_INIT_R 136 select BOARD_EARLY_INIT_F 137 imply PANIC_HANG 138 139config FSL_LSCH2 140 bool 141 select SYS_FSL_HAS_CCI400 142 select SYS_FSL_HAS_SEC 143 select SYS_FSL_SEC_COMPAT_5 144 select SYS_FSL_SEC_BE 145 select SYS_FSL_SRDS_1 146 select SYS_HAS_SERDES 147 148config FSL_LSCH3 149 bool 150 select SYS_FSL_SRDS_1 151 select SYS_HAS_SERDES 152 153config FSL_MC_ENET 154 bool "Management Complex network" 155 depends on ARCH_LS2080A || ARCH_LS1088A 156 default y 157 select RESV_RAM 158 help 159 Enable Management Complex (MC) network 160 161menu "Layerscape architecture" 162 depends on FSL_LSCH2 || FSL_LSCH3 163 164config FSL_PCIE_COMPAT 165 string "PCIe compatible of Kernel DT" 166 depends on PCIE_LAYERSCAPE 167 default "fsl,ls1012a-pcie" if ARCH_LS1012A 168 default "fsl,ls1043a-pcie" if ARCH_LS1043A 169 default "fsl,ls1046a-pcie" if ARCH_LS1046A 170 default "fsl,ls2080a-pcie" if ARCH_LS2080A 171 default "fsl,ls1088a-pcie" if ARCH_LS1088A 172 help 173 This compatible is used to find pci controller node in Kernel DT 174 to complete fixup. 175 176config HAS_FEATURE_GIC64K_ALIGN 177 bool 178 default y if ARCH_LS1043A 179 180config HAS_FEATURE_ENHANCED_MSI 181 bool 182 default y if ARCH_LS1043A 183 184menu "Layerscape PPA" 185config FSL_LS_PPA 186 bool "FSL Layerscape PPA firmware support" 187 depends on !ARMV8_PSCI 188 select ARMV8_SEC_FIRMWARE_SUPPORT 189 select SEC_FIRMWARE_ARMV8_PSCI 190 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 191 help 192 The FSL Primary Protected Application (PPA) is a software component 193 which is loaded during boot stage, and then remains resident in RAM 194 and runs in the TrustZone after boot. 195 Say y to enable it. 196 197config SPL_FSL_LS_PPA 198 bool "FSL Layerscape PPA firmware support for SPL build" 199 depends on !ARMV8_PSCI 200 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 201 select SEC_FIRMWARE_ARMV8_PSCI 202 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 203 help 204 The FSL Primary Protected Application (PPA) is a software component 205 which is loaded during boot stage, and then remains resident in RAM 206 and runs in the TrustZone after boot. This is to load PPA during SPL 207 stage instead of the RAM version of U-Boot. Once PPA is initialized, 208 the rest of U-Boot (including RAM version) runs at EL2. 209choice 210 prompt "FSL Layerscape PPA firmware loading-media select" 211 depends on FSL_LS_PPA 212 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 213 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 214 default SYS_LS_PPA_FW_IN_XIP 215 216config SYS_LS_PPA_FW_IN_XIP 217 bool "XIP" 218 help 219 Say Y here if the PPA firmware locate at XIP flash, such 220 as NOR or QSPI flash. 221 222config SYS_LS_PPA_FW_IN_MMC 223 bool "eMMC or SD Card" 224 help 225 Say Y here if the PPA firmware locate at eMMC/SD card. 226 227config SYS_LS_PPA_FW_IN_NAND 228 bool "NAND" 229 help 230 Say Y here if the PPA firmware locate at NAND flash. 231 232endchoice 233 234config SYS_LS_PPA_FW_ADDR 235 hex "Address of PPA firmware loading from" 236 depends on FSL_LS_PPA 237 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 238 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 239 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 240 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 241 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 242 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 243 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 244 245 help 246 If the PPA firmware locate at XIP flash, such as NOR or 247 QSPI flash, this address is a directly memory-mapped. 248 If it is in a serial accessed flash, such as NAND and SD 249 card, it is a byte offset. 250 251config SYS_LS_PPA_ESBC_ADDR 252 hex "hdr address of PPA firmware loading from" 253 depends on FSL_LS_PPA && CHAIN_OF_TRUST 254 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 255 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 256 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 257 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 258 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 259 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 260 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 261 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 262 help 263 If the PPA header firmware locate at XIP flash, such as NOR or 264 QSPI flash, this address is a directly memory-mapped. 265 If it is in a serial accessed flash, such as NAND and SD 266 card, it is a byte offset. 267 268config LS_PPA_ESBC_HDR_SIZE 269 hex "Length of PPA ESBC header" 270 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 271 default 0x2000 272 help 273 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 274 NAND to memory to validate PPA image. 275 276endmenu 277 278config SYS_FSL_ERRATUM_A008997 279 bool "Workaround for USB PHY erratum A008997" 280 281config SYS_FSL_ERRATUM_A009007 282 bool 283 help 284 Workaround for USB PHY erratum A009007 285 286config SYS_FSL_ERRATUM_A009008 287 bool "Workaround for USB PHY erratum A009008" 288 289config SYS_FSL_ERRATUM_A009798 290 bool "Workaround for USB PHY erratum A009798" 291 292config SYS_FSL_ERRATUM_A010315 293 bool "Workaround for PCIe erratum A010315" 294 295config SYS_FSL_ERRATUM_A010539 296 bool "Workaround for PIN MUX erratum A010539" 297 298config MAX_CPUS 299 int "Maximum number of CPUs permitted for Layerscape" 300 default 4 if ARCH_LS1043A 301 default 4 if ARCH_LS1046A 302 default 16 if ARCH_LS2080A 303 default 8 if ARCH_LS1088A 304 default 1 305 help 306 Set this number to the maximum number of possible CPUs in the SoC. 307 SoCs may have multiple clusters with each cluster may have multiple 308 ports. If some ports are reserved but higher ports are used for 309 cores, count the reserved ports. This will allocate enough memory 310 in spin table to properly handle all cores. 311 312config SECURE_BOOT 313 bool "Secure Boot" 314 help 315 Enable Freescale Secure Boot feature 316 317config QSPI_AHB_INIT 318 bool "Init the QSPI AHB bus" 319 help 320 The default setting for QSPI AHB bus just support 3bytes addressing. 321 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 322 bus for those flashes to support the full QSPI flash size. 323 324config SYS_CCI400_OFFSET 325 hex "Offset for CCI400 base" 326 depends on SYS_FSL_HAS_CCI400 327 default 0x3090000 if ARCH_LS1088A 328 default 0x180000 if FSL_LSCH2 329 help 330 Offset for CCI400 base 331 CCI400 base addr = CCSRBAR + CCI400_OFFSET 332 333config SYS_FSL_IFC_BANK_COUNT 334 int "Maximum banks of Integrated flash controller" 335 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 336 default 4 if ARCH_LS1043A 337 default 4 if ARCH_LS1046A 338 default 8 if ARCH_LS2080A || ARCH_LS1088A 339 340config SYS_FSL_HAS_CCI400 341 bool 342 343config SYS_FSL_HAS_CCN504 344 bool 345 346config SYS_FSL_HAS_DP_DDR 347 bool 348 349config SYS_FSL_SRDS_1 350 bool 351 352config SYS_FSL_SRDS_2 353 bool 354 355config SYS_HAS_SERDES 356 bool 357 358config FSL_TZASC_1 359 bool 360 361config FSL_TZASC_2 362 bool 363 364endmenu 365 366menu "Layerscape clock tree configuration" 367 depends on FSL_LSCH2 || FSL_LSCH3 368 369config SYS_FSL_CLK 370 bool "Enable clock tree initialization" 371 default y 372 373config CLUSTER_CLK_FREQ 374 int "Reference clock of core cluster" 375 depends on ARCH_LS1012A 376 default 100000000 377 help 378 This number is the reference clock frequency of core PLL. 379 For most platforms, the core PLL and Platform PLL have the same 380 reference clock, but for some platforms, LS1012A for instance, 381 they are provided sepatately. 382 383config SYS_FSL_PCLK_DIV 384 int "Platform clock divider" 385 default 1 if ARCH_LS1043A 386 default 1 if ARCH_LS1046A 387 default 1 if ARCH_LS1088A 388 default 2 389 help 390 This is the divider that is used to derive Platform clock from 391 Platform PLL, in another word: 392 Platform_clk = Platform_PLL_freq / this_divider 393 394config SYS_FSL_DSPI_CLK_DIV 395 int "DSPI clock divider" 396 default 1 if ARCH_LS1043A 397 default 2 398 help 399 This is the divider that is used to derive DSPI clock from Platform 400 clock, in another word DSPI_clk = Platform_clk / this_divider. 401 402config SYS_FSL_DUART_CLK_DIV 403 int "DUART clock divider" 404 default 1 if ARCH_LS1043A 405 default 2 406 help 407 This is the divider that is used to derive DUART clock from Platform 408 clock, in another word DUART_clk = Platform_clk / this_divider. 409 410config SYS_FSL_I2C_CLK_DIV 411 int "I2C clock divider" 412 default 1 if ARCH_LS1043A 413 default 2 414 help 415 This is the divider that is used to derive I2C clock from Platform 416 clock, in another word I2C_clk = Platform_clk / this_divider. 417 418config SYS_FSL_IFC_CLK_DIV 419 int "IFC clock divider" 420 default 1 if ARCH_LS1043A 421 default 2 422 help 423 This is the divider that is used to derive IFC clock from Platform 424 clock, in another word IFC_clk = Platform_clk / this_divider. 425 426config SYS_FSL_LPUART_CLK_DIV 427 int "LPUART clock divider" 428 default 1 if ARCH_LS1043A 429 default 2 430 help 431 This is the divider that is used to derive LPUART clock from Platform 432 clock, in another word LPUART_clk = Platform_clk / this_divider. 433 434config SYS_FSL_SDHC_CLK_DIV 435 int "SDHC clock divider" 436 default 1 if ARCH_LS1043A 437 default 1 if ARCH_LS1012A 438 default 2 439 help 440 This is the divider that is used to derive SDHC clock from Platform 441 clock, in another word SDHC_clk = Platform_clk / this_divider. 442endmenu 443 444config RESV_RAM 445 bool 446 help 447 Reserve memory from the top, tracked by gd->arch.resv_ram. This 448 reserved RAM can be used by special driver that resides in memory 449 after U-Boot exits. It's up to implementation to allocate and allow 450 access to this reserved memory. For example, the reserved RAM can 451 be at the high end of physical memory. The reserve RAM may be 452 excluded from memory bank(s) passed to OS, or marked as reserved. 453 454config SYS_FSL_EC1 455 bool 456 help 457 Ethernet controller 1, this is connected to MAC3. 458 Provides DPAA2 capabilities 459 460config SYS_FSL_EC2 461 bool 462 help 463 Ethernet controller 2, this is connected to MAC4. 464 Provides DPAA2 capabilities 465 466config SYS_FSL_ERRATUM_A008336 467 bool 468 469config SYS_FSL_ERRATUM_A008514 470 bool 471 472config SYS_FSL_ERRATUM_A008585 473 bool 474 475config SYS_FSL_ERRATUM_A008850 476 bool 477 478config SYS_FSL_ERRATUM_A009203 479 bool 480 481config SYS_FSL_ERRATUM_A009635 482 bool 483 484config SYS_FSL_ERRATUM_A009660 485 bool 486 487config SYS_FSL_ERRATUM_A009929 488 bool 489 490 491config SYS_FSL_HAS_RGMII 492 bool 493 depends on SYS_FSL_EC1 || SYS_FSL_EC2 494 495 496config SYS_MC_RSV_MEM_ALIGN 497 hex "Management Complex reserved memory alignment" 498 depends on RESV_RAM 499 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A 500 help 501 Reserved memory needs to be aligned for MC to use. Default value 502 is 512MB. 503 504config SPL_LDSCRIPT 505 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 506 507config HAS_FSL_XHCI_USB 508 bool 509 default y if ARCH_LS1043A || ARCH_LS1046A 510 help 511 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 512 pins, select it when the pins are assigned to USB. 513