1config ARCH_LS1012A 2 bool 3 select FSL_LSCH2 4 select SYS_FSL_DDR_BE 5 select SYS_FSL_MMDC 6 select SYS_FSL_ERRATUM_A010315 7 8config ARCH_LS1043A 9 bool 10 select FSL_LSCH2 11 select SYS_FSL_DDR_BE 12 select SYS_FSL_DDR_VER_50 13 select SYS_FSL_ERRATUM_A010315 14 select SYS_FSL_ERRATUM_A010539 15 16config ARCH_LS1046A 17 bool 18 select FSL_LSCH2 19 select SYS_FSL_DDR_BE 20 select SYS_FSL_DDR4 21 select SYS_FSL_DDR_VER_50 22 select SYS_FSL_ERRATUM_A010539 23 select SYS_FSL_SRDS_2 24 25config ARCH_LS2080A 26 bool 27 select FSL_LSCH3 28 select SYS_FSL_DDR4 29 select SYS_FSL_DDR_LE 30 select SYS_FSL_DDR_VER_50 31 select SYS_FSL_HAS_DP_DDR 32 select SYS_FSL_SRDS_2 33 34config FSL_LSCH2 35 bool 36 select SYS_FSL_SRDS_1 37 select SYS_HAS_SERDES 38 39config FSL_LSCH3 40 bool 41 select SYS_FSL_SRDS_1 42 select SYS_HAS_SERDES 43 44menu "Layerscape architecture" 45 depends on FSL_LSCH2 || FSL_LSCH3 46 47menu "Layerscape PPA" 48config FSL_LS_PPA 49 bool "FSL Layerscape PPA firmware support" 50 depends on !ARMV8_PSCI 51 depends on ARCH_LS1043A || ARCH_LS1046A 52 select FSL_PPA_ARMV8_PSCI 53 help 54 The FSL Primary Protected Application (PPA) is a software component 55 which is loaded during boot stage, and then remains resident in RAM 56 and runs in the TrustZone after boot. 57 Say y to enable it. 58 59config FSL_PPA_ARMV8_PSCI 60 bool "PSCI implementation in PPA firmware" 61 depends on FSL_LS_PPA 62 help 63 This config enables the ARMv8 PSCI implementation in PPA firmware. 64 This is a private PSCI implementation and different from those 65 implemented under the common ARMv8 PSCI framework. 66endmenu 67 68config SYS_FSL_MMDC 69 bool 70 71config SYS_FSL_ERRATUM_A010315 72 bool "Workaround for PCIe erratum A010315" 73 74config SYS_FSL_ERRATUM_A010539 75 bool "Workaround for PIN MUX erratum A010539" 76 77config MAX_CPUS 78 int "Maximum number of CPUs permitted for Layerscape" 79 default 4 if ARCH_LS1043A 80 default 4 if ARCH_LS1046A 81 default 16 if ARCH_LS2080A 82 default 1 83 help 84 Set this number to the maximum number of possible CPUs in the SoC. 85 SoCs may have multiple clusters with each cluster may have multiple 86 ports. If some ports are reserved but higher ports are used for 87 cores, count the reserved ports. This will allocate enough memory 88 in spin table to properly handle all cores. 89 90config NUM_DDR_CONTROLLERS 91 int "Maximum DDR controllers" 92 default 3 if ARCH_LS2080A 93 default 1 94 95config SECURE_BOOT 96 bool 97 help 98 Enable Freescale Secure Boot feature 99 100config QSPI_AHB_INIT 101 bool "Init the QSPI AHB bus" 102 help 103 The default setting for QSPI AHB bus just support 3bytes addressing. 104 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 105 bus for those flashes to support the full QSPI flash size. 106 107config SYS_FSL_IFC_BANK_COUNT 108 int "Maximum banks of Integrated flash controller" 109 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 110 default 4 if ARCH_LS1043A 111 default 4 if ARCH_LS1046A 112 default 8 if ARCH_LS2080A 113 114config SYS_FSL_HAS_DP_DDR 115 bool 116 117config SYS_FSL_SRDS_1 118 bool 119 120config SYS_FSL_SRDS_2 121 bool 122 123config SYS_HAS_SERDES 124 bool 125 126config SYS_FSL_DDR 127 bool "Freescale DDR driver" 128 help 129 Select Freescale General DDR driver, shared between most Freescale 130 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- 131 based Layerscape SoCs (such as ls2080a). 132 133config SYS_FSL_DDR_BE 134 bool 135 help 136 Access DDR registers in big-endian. 137 138config SYS_FSL_DDR_LE 139 bool 140 help 141 Access DDR registers in little-endian. 142 143config SYS_FSL_DDR_VER 144 int 145 default 50 if SYS_FSL_DDR_VER_50 146 147config SYS_FSL_DDR_VER_50 148 bool 149 150config SYS_FSL_DDRC_ARM_GEN3 151 bool 152 153config SYS_FSL_DDRC_GEN4 154 bool 155 156config SYS_FSL_DDR3 157 bool "Freescale DDR3 controller" 158 depends on !SYS_FSL_DDR4 159 select SYS_FSL_DDR 160 select SYS_FSL_DDRC_ARM_GEN3 161 help 162 Enable Freescale DDR3 controller on ARM-based SoCs. 163 164config SYS_FSL_DDR4 165 bool "Freescale DDR4 controller" 166 select SYS_FSL_DDR 167 select SYS_FSL_DDRC_GEN4 168 help 169 Enable Freescale DDR4 controller. 170 171endmenu 172