1config ARCH_LS1012A
2	bool
3	select FSL_LSCH2
4	select SYS_FSL_DDR_BE
5	select SYS_FSL_MMDC
6	select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
9	bool
10	select FSL_LSCH2
11	select SYS_FSL_DDR
12	select SYS_FSL_DDR_BE
13	select SYS_FSL_DDR_VER_50
14	select SYS_FSL_ERRATUM_A010315
15	select SYS_FSL_ERRATUM_A010539
16	select SYS_FSL_HAS_DDR3
17	select SYS_FSL_HAS_DDR4
18
19config ARCH_LS1046A
20	bool
21	select FSL_LSCH2
22	select SYS_FSL_DDR
23	select SYS_FSL_DDR_BE
24	select SYS_FSL_DDR_VER_50
25	select SYS_FSL_ERRATUM_A010539
26	select SYS_FSL_HAS_DDR4
27	select SYS_FSL_SRDS_2
28
29config ARCH_LS2080A
30	bool
31	select FSL_LSCH3
32	select SYS_FSL_DDR
33	select SYS_FSL_DDR_LE
34	select SYS_FSL_DDR_VER_50
35	select SYS_FSL_HAS_DP_DDR
36	select SYS_FSL_HAS_SEC
37	select SYS_FSL_HAS_DDR4
38	select SYS_FSL_SEC_COMPAT_5
39	select SYS_FSL_SEC_LE
40	select SYS_FSL_SRDS_2
41
42config FSL_LSCH2
43	bool
44	select SYS_FSL_HAS_SEC
45	select SYS_FSL_SEC_COMPAT_5
46	select SYS_FSL_SEC_BE
47	select SYS_FSL_SRDS_1
48	select SYS_HAS_SERDES
49
50config FSL_LSCH3
51	bool
52	select SYS_FSL_SRDS_1
53	select SYS_HAS_SERDES
54
55menu "Layerscape architecture"
56	depends on FSL_LSCH2 || FSL_LSCH3
57
58menu "Layerscape PPA"
59config FSL_LS_PPA
60	bool "FSL Layerscape PPA firmware support"
61	depends on !ARMV8_PSCI
62	depends on ARCH_LS1043A || ARCH_LS1046A
63	select FSL_PPA_ARMV8_PSCI
64	help
65	  The FSL Primary Protected Application (PPA) is a software component
66	  which is loaded during boot stage, and then remains resident in RAM
67	  and runs in the TrustZone after boot.
68	  Say y to enable it.
69
70config FSL_PPA_ARMV8_PSCI
71	bool "PSCI implementation in PPA firmware"
72	depends on FSL_LS_PPA
73	help
74	  This config enables the ARMv8 PSCI implementation in PPA firmware.
75	  This is a private PSCI implementation and different from those
76	  implemented under the common ARMv8 PSCI framework.
77endmenu
78
79config SYS_FSL_ERRATUM_A010315
80	bool "Workaround for PCIe erratum A010315"
81
82config SYS_FSL_ERRATUM_A010539
83	bool "Workaround for PIN MUX erratum A010539"
84
85config MAX_CPUS
86	int "Maximum number of CPUs permitted for Layerscape"
87	default 4 if ARCH_LS1043A
88	default 4 if ARCH_LS1046A
89	default 16 if ARCH_LS2080A
90	default 1
91	help
92	  Set this number to the maximum number of possible CPUs in the SoC.
93	  SoCs may have multiple clusters with each cluster may have multiple
94	  ports. If some ports are reserved but higher ports are used for
95	  cores, count the reserved ports. This will allocate enough memory
96	  in spin table to properly handle all cores.
97
98config NUM_DDR_CONTROLLERS
99	int "Maximum DDR controllers"
100	default 3 if ARCH_LS2080A
101	default 1
102
103config SECURE_BOOT
104	bool
105	help
106		Enable Freescale Secure Boot feature
107
108config QSPI_AHB_INIT
109	bool "Init the QSPI AHB bus"
110	help
111	  The default setting for QSPI AHB bus just support 3bytes addressing.
112	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
113	  bus for those flashes to support the full QSPI flash size.
114
115config SYS_FSL_IFC_BANK_COUNT
116	int "Maximum banks of Integrated flash controller"
117	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
118	default 4 if ARCH_LS1043A
119	default 4 if ARCH_LS1046A
120	default 8 if ARCH_LS2080A
121
122config SYS_FSL_HAS_DP_DDR
123	bool
124
125config SYS_FSL_SRDS_1
126	bool
127
128config SYS_FSL_SRDS_2
129	bool
130
131config SYS_HAS_SERDES
132	bool
133
134endmenu
135