1config ARCH_LS1012A
2	bool
3	select ARMV8_SET_SMPEN
4	select FSL_LSCH2
5	select SYS_FSL_DDR_BE
6	select SYS_FSL_MMDC
7	select SYS_FSL_ERRATUM_A010315
8	select ARCH_EARLY_INIT_R
9	select BOARD_EARLY_INIT_F
10
11config ARCH_LS1043A
12	bool
13	select ARMV8_SET_SMPEN
14	select FSL_LSCH2
15	select SYS_FSL_DDR
16	select SYS_FSL_DDR_BE
17	select SYS_FSL_DDR_VER_50
18	select SYS_FSL_ERRATUM_A008850
19	select SYS_FSL_ERRATUM_A008997
20	select SYS_FSL_ERRATUM_A009007
21	select SYS_FSL_ERRATUM_A009008
22	select SYS_FSL_ERRATUM_A009660
23	select SYS_FSL_ERRATUM_A009663
24	select SYS_FSL_ERRATUM_A009798
25	select SYS_FSL_ERRATUM_A009929
26	select SYS_FSL_ERRATUM_A009942
27	select SYS_FSL_ERRATUM_A010315
28	select SYS_FSL_ERRATUM_A010539
29	select SYS_FSL_HAS_DDR3
30	select SYS_FSL_HAS_DDR4
31	select ARCH_EARLY_INIT_R
32	select BOARD_EARLY_INIT_F
33	imply SCSI
34	imply CMD_PCI
35
36config ARCH_LS1046A
37	bool
38	select ARMV8_SET_SMPEN
39	select FSL_LSCH2
40	select SYS_FSL_DDR
41	select SYS_FSL_DDR_BE
42	select SYS_FSL_DDR_VER_50
43	select SYS_FSL_ERRATUM_A008336
44	select SYS_FSL_ERRATUM_A008511
45	select SYS_FSL_ERRATUM_A008850
46	select SYS_FSL_ERRATUM_A008997
47	select SYS_FSL_ERRATUM_A009007
48	select SYS_FSL_ERRATUM_A009008
49	select SYS_FSL_ERRATUM_A009798
50	select SYS_FSL_ERRATUM_A009801
51	select SYS_FSL_ERRATUM_A009803
52	select SYS_FSL_ERRATUM_A009942
53	select SYS_FSL_ERRATUM_A010165
54	select SYS_FSL_ERRATUM_A010539
55	select SYS_FSL_HAS_DDR4
56	select SYS_FSL_SRDS_2
57	select ARCH_EARLY_INIT_R
58	select BOARD_EARLY_INIT_F
59	imply SCSI
60
61config ARCH_LS1088A
62	bool
63	select ARMV8_SET_SMPEN
64	select FSL_LSCH3
65	select SYS_FSL_DDR
66	select SYS_FSL_DDR_LE
67	select SYS_FSL_DDR_VER_50
68	select SYS_FSL_EC1
69	select SYS_FSL_EC2
70	select SYS_FSL_ERRATUM_A009803
71	select SYS_FSL_ERRATUM_A009942
72	select SYS_FSL_ERRATUM_A010165
73	select SYS_FSL_ERRATUM_A008511
74	select SYS_FSL_ERRATUM_A008850
75	select SYS_FSL_ERRATUM_A009007
76	select SYS_FSL_HAS_CCI400
77	select SYS_FSL_HAS_DDR4
78	select SYS_FSL_HAS_RGMII
79	select SYS_FSL_HAS_SEC
80	select SYS_FSL_SEC_COMPAT_5
81	select SYS_FSL_SEC_LE
82	select SYS_FSL_SRDS_1
83	select SYS_FSL_SRDS_2
84	select FSL_TZASC_1
85	select ARCH_EARLY_INIT_R
86	select BOARD_EARLY_INIT_F
87
88config ARCH_LS2080A
89	bool
90	select ARMV8_SET_SMPEN
91	select ARM_ERRATA_826974
92	select ARM_ERRATA_828024
93	select ARM_ERRATA_829520
94	select ARM_ERRATA_833471
95	select FSL_LSCH3
96	select SYS_FSL_DDR
97	select SYS_FSL_DDR_LE
98	select SYS_FSL_DDR_VER_50
99	select SYS_FSL_HAS_CCN504
100	select SYS_FSL_HAS_DP_DDR
101	select SYS_FSL_HAS_SEC
102	select SYS_FSL_HAS_DDR4
103	select SYS_FSL_SEC_COMPAT_5
104	select SYS_FSL_SEC_LE
105	select SYS_FSL_SRDS_2
106	select FSL_TZASC_1
107	select FSL_TZASC_2
108	select SYS_FSL_ERRATUM_A008336
109	select SYS_FSL_ERRATUM_A008511
110	select SYS_FSL_ERRATUM_A008514
111	select SYS_FSL_ERRATUM_A008585
112	select SYS_FSL_ERRATUM_A008997
113	select SYS_FSL_ERRATUM_A009007
114	select SYS_FSL_ERRATUM_A009008
115	select SYS_FSL_ERRATUM_A009635
116	select SYS_FSL_ERRATUM_A009663
117	select SYS_FSL_ERRATUM_A009798
118	select SYS_FSL_ERRATUM_A009801
119	select SYS_FSL_ERRATUM_A009803
120	select SYS_FSL_ERRATUM_A009942
121	select SYS_FSL_ERRATUM_A010165
122	select SYS_FSL_ERRATUM_A009203
123	select ARCH_EARLY_INIT_R
124	select BOARD_EARLY_INIT_F
125
126config FSL_LSCH2
127	bool
128	select SYS_FSL_HAS_CCI400
129	select SYS_FSL_HAS_SEC
130	select SYS_FSL_SEC_COMPAT_5
131	select SYS_FSL_SEC_BE
132	select SYS_FSL_SRDS_1
133	select SYS_HAS_SERDES
134
135config FSL_LSCH3
136	bool
137	select SYS_FSL_SRDS_1
138	select SYS_HAS_SERDES
139
140config FSL_MC_ENET
141	bool "Management Complex network"
142	depends on ARCH_LS2080A || ARCH_LS1088A
143	default y
144	select RESV_RAM
145	help
146	  Enable Management Complex (MC) network
147
148menu "Layerscape architecture"
149	depends on FSL_LSCH2 || FSL_LSCH3
150
151config FSL_PCIE_COMPAT
152	string "PCIe compatible of Kernel DT"
153	depends on PCIE_LAYERSCAPE
154	default "fsl,ls1012a-pcie" if ARCH_LS1012A
155	default "fsl,ls1043a-pcie" if ARCH_LS1043A
156	default "fsl,ls1046a-pcie" if ARCH_LS1046A
157	default "fsl,ls2080a-pcie" if ARCH_LS2080A
158	default "fsl,ls1088a-pcie" if ARCH_LS1088A
159	help
160	  This compatible is used to find pci controller node in Kernel DT
161	  to complete fixup.
162
163config HAS_FEATURE_GIC64K_ALIGN
164	bool
165	default y if ARCH_LS1043A
166
167config HAS_FEATURE_ENHANCED_MSI
168	bool
169	default y if ARCH_LS1043A
170
171menu "Layerscape PPA"
172config FSL_LS_PPA
173	bool "FSL Layerscape PPA firmware support"
174	depends on !ARMV8_PSCI
175	select ARMV8_SEC_FIRMWARE_SUPPORT
176	select SEC_FIRMWARE_ARMV8_PSCI
177	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
178	help
179	  The FSL Primary Protected Application (PPA) is a software component
180	  which is loaded during boot stage, and then remains resident in RAM
181	  and runs in the TrustZone after boot.
182	  Say y to enable it.
183
184config SPL_FSL_LS_PPA
185	bool "FSL Layerscape PPA firmware support for SPL build"
186	depends on !ARMV8_PSCI
187	select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
188	select SEC_FIRMWARE_ARMV8_PSCI
189	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
190	help
191	  The FSL Primary Protected Application (PPA) is a software component
192	  which is loaded during boot stage, and then remains resident in RAM
193	  and runs in the TrustZone after boot. This is to load PPA during SPL
194	  stage instead of the RAM version of U-Boot. Once PPA is initialized,
195	  the rest of U-Boot (including RAM version) runs at EL2.
196choice
197	prompt "FSL Layerscape PPA firmware loading-media select"
198	depends on FSL_LS_PPA
199	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
200	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
201	default SYS_LS_PPA_FW_IN_XIP
202
203config SYS_LS_PPA_FW_IN_XIP
204	bool "XIP"
205	help
206	  Say Y here if the PPA firmware locate at XIP flash, such
207	  as NOR or QSPI flash.
208
209config SYS_LS_PPA_FW_IN_MMC
210	bool "eMMC or SD Card"
211	help
212	  Say Y here if the PPA firmware locate at eMMC/SD card.
213
214config SYS_LS_PPA_FW_IN_NAND
215	bool "NAND"
216	help
217	  Say Y here if the PPA firmware locate at NAND flash.
218
219endchoice
220
221config SYS_LS_PPA_FW_ADDR
222	hex "Address of PPA firmware loading from"
223	depends on FSL_LS_PPA
224	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
225	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
226	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
227	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
228	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
229	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
230	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
231
232	help
233	  If the PPA firmware locate at XIP flash, such as NOR or
234	  QSPI flash, this address is a directly memory-mapped.
235	  If it is in a serial accessed flash, such as NAND and SD
236	  card, it is a byte offset.
237
238config SYS_LS_PPA_ESBC_ADDR
239	hex "hdr address of PPA firmware loading from"
240	depends on FSL_LS_PPA && CHAIN_OF_TRUST
241	default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
242	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
243	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
244	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
245	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
246	default 0x680000 if SYS_LS_PPA_FW_IN_MMC
247	default 0x680000 if SYS_LS_PPA_FW_IN_NAND
248	help
249	  If the PPA header firmware locate at XIP flash, such as NOR or
250	  QSPI flash, this address is a directly memory-mapped.
251	  If it is in a serial accessed flash, such as NAND and SD
252	  card, it is a byte offset.
253
254config LS_PPA_ESBC_HDR_SIZE
255	hex "Length of PPA ESBC header"
256	depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
257	default 0x2000
258	help
259	  Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
260	  NAND to memory to validate PPA image.
261
262endmenu
263
264config SYS_FSL_ERRATUM_A008997
265	bool "Workaround for USB PHY erratum A008997"
266
267config SYS_FSL_ERRATUM_A009007
268	bool
269	help
270	  Workaround for USB PHY erratum A009007
271
272config SYS_FSL_ERRATUM_A009008
273	bool "Workaround for USB PHY erratum A009008"
274
275config SYS_FSL_ERRATUM_A009798
276	bool "Workaround for USB PHY erratum A009798"
277
278config SYS_FSL_ERRATUM_A010315
279	bool "Workaround for PCIe erratum A010315"
280
281config SYS_FSL_ERRATUM_A010539
282	bool "Workaround for PIN MUX erratum A010539"
283
284config MAX_CPUS
285	int "Maximum number of CPUs permitted for Layerscape"
286	default 4 if ARCH_LS1043A
287	default 4 if ARCH_LS1046A
288	default 16 if ARCH_LS2080A
289	default 8 if ARCH_LS1088A
290	default 1
291	help
292	  Set this number to the maximum number of possible CPUs in the SoC.
293	  SoCs may have multiple clusters with each cluster may have multiple
294	  ports. If some ports are reserved but higher ports are used for
295	  cores, count the reserved ports. This will allocate enough memory
296	  in spin table to properly handle all cores.
297
298config SECURE_BOOT
299	bool "Secure Boot"
300	help
301		Enable Freescale Secure Boot feature
302
303config QSPI_AHB_INIT
304	bool "Init the QSPI AHB bus"
305	help
306	  The default setting for QSPI AHB bus just support 3bytes addressing.
307	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
308	  bus for those flashes to support the full QSPI flash size.
309
310config SYS_CCI400_OFFSET
311	hex "Offset for CCI400 base"
312	depends on SYS_FSL_HAS_CCI400
313	default 0x3090000 if ARCH_LS1088A
314	default 0x180000 if FSL_LSCH2
315	help
316	  Offset for CCI400 base
317	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
318
319config SYS_FSL_IFC_BANK_COUNT
320	int "Maximum banks of Integrated flash controller"
321	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
322	default 4 if ARCH_LS1043A
323	default 4 if ARCH_LS1046A
324	default 8 if ARCH_LS2080A || ARCH_LS1088A
325
326config SYS_FSL_HAS_CCI400
327	bool
328
329config SYS_FSL_HAS_CCN504
330	bool
331
332config SYS_FSL_HAS_DP_DDR
333	bool
334
335config SYS_FSL_SRDS_1
336	bool
337
338config SYS_FSL_SRDS_2
339	bool
340
341config SYS_HAS_SERDES
342	bool
343
344config FSL_TZASC_1
345	bool
346
347config FSL_TZASC_2
348	bool
349
350endmenu
351
352menu "Layerscape clock tree configuration"
353	depends on FSL_LSCH2 || FSL_LSCH3
354
355config SYS_FSL_CLK
356	bool "Enable clock tree initialization"
357	default y
358
359config CLUSTER_CLK_FREQ
360	int "Reference clock of core cluster"
361	depends on ARCH_LS1012A
362	default 100000000
363	help
364	  This number is the reference clock frequency of core PLL.
365	  For most platforms, the core PLL and Platform PLL have the same
366	  reference clock, but for some platforms, LS1012A for instance,
367	  they are provided sepatately.
368
369config SYS_FSL_PCLK_DIV
370	int "Platform clock divider"
371	default 1 if ARCH_LS1043A
372	default 1 if ARCH_LS1046A
373	default 1 if ARCH_LS1088A
374	default 2
375	help
376	  This is the divider that is used to derive Platform clock from
377	  Platform PLL, in another word:
378		Platform_clk = Platform_PLL_freq / this_divider
379
380config SYS_FSL_DSPI_CLK_DIV
381	int "DSPI clock divider"
382	default 1 if ARCH_LS1043A
383	default 2
384	help
385	  This is the divider that is used to derive DSPI clock from Platform
386	  clock, in another word DSPI_clk = Platform_clk / this_divider.
387
388config SYS_FSL_DUART_CLK_DIV
389	int "DUART clock divider"
390	default 1 if ARCH_LS1043A
391	default 2
392	help
393	  This is the divider that is used to derive DUART clock from Platform
394	  clock, in another word DUART_clk = Platform_clk / this_divider.
395
396config SYS_FSL_I2C_CLK_DIV
397	int "I2C clock divider"
398	default 1 if ARCH_LS1043A
399	default 2
400	help
401	  This is the divider that is used to derive I2C clock from Platform
402	  clock, in another word I2C_clk = Platform_clk / this_divider.
403
404config SYS_FSL_IFC_CLK_DIV
405	int "IFC clock divider"
406	default 1 if ARCH_LS1043A
407	default 2
408	help
409	  This is the divider that is used to derive IFC clock from Platform
410	  clock, in another word IFC_clk = Platform_clk / this_divider.
411
412config SYS_FSL_LPUART_CLK_DIV
413	int "LPUART clock divider"
414	default 1 if ARCH_LS1043A
415	default 2
416	help
417	  This is the divider that is used to derive LPUART clock from Platform
418	  clock, in another word LPUART_clk = Platform_clk / this_divider.
419
420config SYS_FSL_SDHC_CLK_DIV
421	int "SDHC clock divider"
422	default 1 if ARCH_LS1043A
423	default 1 if ARCH_LS1012A
424	default 2
425	help
426	  This is the divider that is used to derive SDHC clock from Platform
427	  clock, in another word SDHC_clk = Platform_clk / this_divider.
428endmenu
429
430config RESV_RAM
431	bool
432	help
433	  Reserve memory from the top, tracked by gd->arch.resv_ram. This
434	  reserved RAM can be used by special driver that resides in memory
435	  after U-Boot exits. It's up to implementation to allocate and allow
436	  access to this reserved memory. For example, the reserved RAM can
437	  be at the high end of physical memory. The reserve RAM may be
438	  excluded from memory bank(s) passed to OS, or marked as reserved.
439
440config SYS_FSL_EC1
441	bool
442	help
443	  Ethernet controller 1, this is connected to MAC3.
444	  Provides DPAA2 capabilities
445
446config SYS_FSL_EC2
447	bool
448	help
449	  Ethernet controller 2, this is connected to MAC4.
450	  Provides DPAA2 capabilities
451
452config SYS_FSL_ERRATUM_A008336
453	bool
454
455config SYS_FSL_ERRATUM_A008514
456	bool
457
458config SYS_FSL_ERRATUM_A008585
459	bool
460
461config SYS_FSL_ERRATUM_A008850
462	bool
463
464config SYS_FSL_ERRATUM_A009203
465	bool
466
467config SYS_FSL_ERRATUM_A009635
468	bool
469
470config SYS_FSL_ERRATUM_A009660
471	bool
472
473config SYS_FSL_ERRATUM_A009929
474	bool
475
476
477config SYS_FSL_HAS_RGMII
478	bool
479	depends on SYS_FSL_EC1 || SYS_FSL_EC2
480
481
482config SYS_MC_RSV_MEM_ALIGN
483	hex "Management Complex reserved memory alignment"
484	depends on RESV_RAM
485	default 0x20000000 if ARCH_LS2080A
486	default 0x70000000 if ARCH_LS1088A
487	help
488	  Reserved memory needs to be aligned for MC to use. Default value
489	  is 512MB.
490
491config SPL_LDSCRIPT
492	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
493
494config HAS_FSL_XHCI_USB
495	bool
496	default y if ARCH_LS1043A || ARCH_LS1046A
497	help
498	  For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
499	  pins, select it when the pins are assigned to USB.
500