1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select SYS_FSL_ERRATUM_A009798 9 select SYS_FSL_ERRATUM_A008997 10 select SYS_FSL_ERRATUM_A009007 11 select SYS_FSL_ERRATUM_A009008 12 select ARCH_EARLY_INIT_R 13 select BOARD_EARLY_INIT_F 14 imply PANIC_HANG 15 16config ARCH_LS1043A 17 bool 18 select ARMV8_SET_SMPEN 19 select FSL_LSCH2 20 select SYS_FSL_DDR 21 select SYS_FSL_DDR_BE 22 select SYS_FSL_DDR_VER_50 23 select SYS_FSL_ERRATUM_A008850 24 select SYS_FSL_ERRATUM_A008997 25 select SYS_FSL_ERRATUM_A009007 26 select SYS_FSL_ERRATUM_A009008 27 select SYS_FSL_ERRATUM_A009660 28 select SYS_FSL_ERRATUM_A009663 29 select SYS_FSL_ERRATUM_A009798 30 select SYS_FSL_ERRATUM_A009929 31 select SYS_FSL_ERRATUM_A009942 32 select SYS_FSL_ERRATUM_A010315 33 select SYS_FSL_ERRATUM_A010539 34 select SYS_FSL_HAS_DDR3 35 select SYS_FSL_HAS_DDR4 36 select ARCH_EARLY_INIT_R 37 select BOARD_EARLY_INIT_F 38 imply SCSI 39 imply SCSI_AHCI 40 imply CMD_PCI 41 42config ARCH_LS1046A 43 bool 44 select ARMV8_SET_SMPEN 45 select FSL_LSCH2 46 select SYS_FSL_DDR 47 select SYS_FSL_DDR_BE 48 select SYS_FSL_DDR_VER_50 49 select SYS_FSL_ERRATUM_A008336 50 select SYS_FSL_ERRATUM_A008511 51 select SYS_FSL_ERRATUM_A008850 52 select SYS_FSL_ERRATUM_A008997 53 select SYS_FSL_ERRATUM_A009007 54 select SYS_FSL_ERRATUM_A009008 55 select SYS_FSL_ERRATUM_A009798 56 select SYS_FSL_ERRATUM_A009801 57 select SYS_FSL_ERRATUM_A009803 58 select SYS_FSL_ERRATUM_A009942 59 select SYS_FSL_ERRATUM_A010165 60 select SYS_FSL_ERRATUM_A010539 61 select SYS_FSL_HAS_DDR4 62 select SYS_FSL_SRDS_2 63 select ARCH_EARLY_INIT_R 64 select BOARD_EARLY_INIT_F 65 imply SCSI 66 imply SCSI_AHCI 67 68config ARCH_LS1088A 69 bool 70 select ARMV8_SET_SMPEN 71 select FSL_LSCH3 72 select SYS_FSL_DDR 73 select SYS_FSL_DDR_LE 74 select SYS_FSL_DDR_VER_50 75 select SYS_FSL_EC1 76 select SYS_FSL_EC2 77 select SYS_FSL_ERRATUM_A009803 78 select SYS_FSL_ERRATUM_A009942 79 select SYS_FSL_ERRATUM_A010165 80 select SYS_FSL_ERRATUM_A008511 81 select SYS_FSL_ERRATUM_A008850 82 select SYS_FSL_ERRATUM_A009007 83 select SYS_FSL_HAS_CCI400 84 select SYS_FSL_HAS_DDR4 85 select SYS_FSL_HAS_RGMII 86 select SYS_FSL_HAS_SEC 87 select SYS_FSL_SEC_COMPAT_5 88 select SYS_FSL_SEC_LE 89 select SYS_FSL_SRDS_1 90 select SYS_FSL_SRDS_2 91 select FSL_TZASC_1 92 select ARCH_EARLY_INIT_R 93 select BOARD_EARLY_INIT_F 94 imply SCSI 95 imply PANIC_HANG 96 97config ARCH_LS2080A 98 bool 99 select ARMV8_SET_SMPEN 100 select ARM_ERRATA_826974 101 select ARM_ERRATA_828024 102 select ARM_ERRATA_829520 103 select ARM_ERRATA_833471 104 select FSL_LSCH3 105 select SYS_FSL_DDR 106 select SYS_FSL_DDR_LE 107 select SYS_FSL_DDR_VER_50 108 select SYS_FSL_HAS_CCN504 109 select SYS_FSL_HAS_DP_DDR 110 select SYS_FSL_HAS_SEC 111 select SYS_FSL_HAS_DDR4 112 select SYS_FSL_SEC_COMPAT_5 113 select SYS_FSL_SEC_LE 114 select SYS_FSL_SRDS_2 115 select FSL_TZASC_1 116 select FSL_TZASC_2 117 select SYS_FSL_ERRATUM_A008336 118 select SYS_FSL_ERRATUM_A008511 119 select SYS_FSL_ERRATUM_A008514 120 select SYS_FSL_ERRATUM_A008585 121 select SYS_FSL_ERRATUM_A008997 122 select SYS_FSL_ERRATUM_A009007 123 select SYS_FSL_ERRATUM_A009008 124 select SYS_FSL_ERRATUM_A009635 125 select SYS_FSL_ERRATUM_A009663 126 select SYS_FSL_ERRATUM_A009798 127 select SYS_FSL_ERRATUM_A009801 128 select SYS_FSL_ERRATUM_A009803 129 select SYS_FSL_ERRATUM_A009942 130 select SYS_FSL_ERRATUM_A010165 131 select SYS_FSL_ERRATUM_A009203 132 select ARCH_EARLY_INIT_R 133 select BOARD_EARLY_INIT_F 134 imply PANIC_HANG 135 136config FSL_LSCH2 137 bool 138 select SYS_FSL_HAS_CCI400 139 select SYS_FSL_HAS_SEC 140 select SYS_FSL_SEC_COMPAT_5 141 select SYS_FSL_SEC_BE 142 select SYS_FSL_SRDS_1 143 select SYS_HAS_SERDES 144 145config FSL_LSCH3 146 bool 147 select SYS_FSL_SRDS_1 148 select SYS_HAS_SERDES 149 150config FSL_MC_ENET 151 bool "Management Complex network" 152 depends on ARCH_LS2080A || ARCH_LS1088A 153 default y 154 select RESV_RAM 155 help 156 Enable Management Complex (MC) network 157 158menu "Layerscape architecture" 159 depends on FSL_LSCH2 || FSL_LSCH3 160 161config FSL_PCIE_COMPAT 162 string "PCIe compatible of Kernel DT" 163 depends on PCIE_LAYERSCAPE 164 default "fsl,ls1012a-pcie" if ARCH_LS1012A 165 default "fsl,ls1043a-pcie" if ARCH_LS1043A 166 default "fsl,ls1046a-pcie" if ARCH_LS1046A 167 default "fsl,ls2080a-pcie" if ARCH_LS2080A 168 default "fsl,ls1088a-pcie" if ARCH_LS1088A 169 help 170 This compatible is used to find pci controller node in Kernel DT 171 to complete fixup. 172 173config HAS_FEATURE_GIC64K_ALIGN 174 bool 175 default y if ARCH_LS1043A 176 177config HAS_FEATURE_ENHANCED_MSI 178 bool 179 default y if ARCH_LS1043A 180 181menu "Layerscape PPA" 182config FSL_LS_PPA 183 bool "FSL Layerscape PPA firmware support" 184 depends on !ARMV8_PSCI 185 select ARMV8_SEC_FIRMWARE_SUPPORT 186 select SEC_FIRMWARE_ARMV8_PSCI 187 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 188 help 189 The FSL Primary Protected Application (PPA) is a software component 190 which is loaded during boot stage, and then remains resident in RAM 191 and runs in the TrustZone after boot. 192 Say y to enable it. 193 194config SPL_FSL_LS_PPA 195 bool "FSL Layerscape PPA firmware support for SPL build" 196 depends on !ARMV8_PSCI 197 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 198 select SEC_FIRMWARE_ARMV8_PSCI 199 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 200 help 201 The FSL Primary Protected Application (PPA) is a software component 202 which is loaded during boot stage, and then remains resident in RAM 203 and runs in the TrustZone after boot. This is to load PPA during SPL 204 stage instead of the RAM version of U-Boot. Once PPA is initialized, 205 the rest of U-Boot (including RAM version) runs at EL2. 206choice 207 prompt "FSL Layerscape PPA firmware loading-media select" 208 depends on FSL_LS_PPA 209 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 210 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 211 default SYS_LS_PPA_FW_IN_XIP 212 213config SYS_LS_PPA_FW_IN_XIP 214 bool "XIP" 215 help 216 Say Y here if the PPA firmware locate at XIP flash, such 217 as NOR or QSPI flash. 218 219config SYS_LS_PPA_FW_IN_MMC 220 bool "eMMC or SD Card" 221 help 222 Say Y here if the PPA firmware locate at eMMC/SD card. 223 224config SYS_LS_PPA_FW_IN_NAND 225 bool "NAND" 226 help 227 Say Y here if the PPA firmware locate at NAND flash. 228 229endchoice 230 231config SYS_LS_PPA_FW_ADDR 232 hex "Address of PPA firmware loading from" 233 depends on FSL_LS_PPA 234 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 235 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 236 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 237 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 238 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 239 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 240 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 241 242 help 243 If the PPA firmware locate at XIP flash, such as NOR or 244 QSPI flash, this address is a directly memory-mapped. 245 If it is in a serial accessed flash, such as NAND and SD 246 card, it is a byte offset. 247 248config SYS_LS_PPA_ESBC_ADDR 249 hex "hdr address of PPA firmware loading from" 250 depends on FSL_LS_PPA && CHAIN_OF_TRUST 251 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 252 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 253 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 254 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 255 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 256 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 257 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 258 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 259 help 260 If the PPA header firmware locate at XIP flash, such as NOR or 261 QSPI flash, this address is a directly memory-mapped. 262 If it is in a serial accessed flash, such as NAND and SD 263 card, it is a byte offset. 264 265config LS_PPA_ESBC_HDR_SIZE 266 hex "Length of PPA ESBC header" 267 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 268 default 0x2000 269 help 270 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 271 NAND to memory to validate PPA image. 272 273endmenu 274 275config SYS_FSL_ERRATUM_A008997 276 bool "Workaround for USB PHY erratum A008997" 277 278config SYS_FSL_ERRATUM_A009007 279 bool 280 help 281 Workaround for USB PHY erratum A009007 282 283config SYS_FSL_ERRATUM_A009008 284 bool "Workaround for USB PHY erratum A009008" 285 286config SYS_FSL_ERRATUM_A009798 287 bool "Workaround for USB PHY erratum A009798" 288 289config SYS_FSL_ERRATUM_A010315 290 bool "Workaround for PCIe erratum A010315" 291 292config SYS_FSL_ERRATUM_A010539 293 bool "Workaround for PIN MUX erratum A010539" 294 295config MAX_CPUS 296 int "Maximum number of CPUs permitted for Layerscape" 297 default 4 if ARCH_LS1043A 298 default 4 if ARCH_LS1046A 299 default 16 if ARCH_LS2080A 300 default 8 if ARCH_LS1088A 301 default 1 302 help 303 Set this number to the maximum number of possible CPUs in the SoC. 304 SoCs may have multiple clusters with each cluster may have multiple 305 ports. If some ports are reserved but higher ports are used for 306 cores, count the reserved ports. This will allocate enough memory 307 in spin table to properly handle all cores. 308 309config SECURE_BOOT 310 bool "Secure Boot" 311 help 312 Enable Freescale Secure Boot feature 313 314config QSPI_AHB_INIT 315 bool "Init the QSPI AHB bus" 316 help 317 The default setting for QSPI AHB bus just support 3bytes addressing. 318 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 319 bus for those flashes to support the full QSPI flash size. 320 321config SYS_CCI400_OFFSET 322 hex "Offset for CCI400 base" 323 depends on SYS_FSL_HAS_CCI400 324 default 0x3090000 if ARCH_LS1088A 325 default 0x180000 if FSL_LSCH2 326 help 327 Offset for CCI400 base 328 CCI400 base addr = CCSRBAR + CCI400_OFFSET 329 330config SYS_FSL_IFC_BANK_COUNT 331 int "Maximum banks of Integrated flash controller" 332 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 333 default 4 if ARCH_LS1043A 334 default 4 if ARCH_LS1046A 335 default 8 if ARCH_LS2080A || ARCH_LS1088A 336 337config SYS_FSL_HAS_CCI400 338 bool 339 340config SYS_FSL_HAS_CCN504 341 bool 342 343config SYS_FSL_HAS_DP_DDR 344 bool 345 346config SYS_FSL_SRDS_1 347 bool 348 349config SYS_FSL_SRDS_2 350 bool 351 352config SYS_HAS_SERDES 353 bool 354 355config FSL_TZASC_1 356 bool 357 358config FSL_TZASC_2 359 bool 360 361endmenu 362 363menu "Layerscape clock tree configuration" 364 depends on FSL_LSCH2 || FSL_LSCH3 365 366config SYS_FSL_CLK 367 bool "Enable clock tree initialization" 368 default y 369 370config CLUSTER_CLK_FREQ 371 int "Reference clock of core cluster" 372 depends on ARCH_LS1012A 373 default 100000000 374 help 375 This number is the reference clock frequency of core PLL. 376 For most platforms, the core PLL and Platform PLL have the same 377 reference clock, but for some platforms, LS1012A for instance, 378 they are provided sepatately. 379 380config SYS_FSL_PCLK_DIV 381 int "Platform clock divider" 382 default 1 if ARCH_LS1043A 383 default 1 if ARCH_LS1046A 384 default 1 if ARCH_LS1088A 385 default 2 386 help 387 This is the divider that is used to derive Platform clock from 388 Platform PLL, in another word: 389 Platform_clk = Platform_PLL_freq / this_divider 390 391config SYS_FSL_DSPI_CLK_DIV 392 int "DSPI clock divider" 393 default 1 if ARCH_LS1043A 394 default 2 395 help 396 This is the divider that is used to derive DSPI clock from Platform 397 clock, in another word DSPI_clk = Platform_clk / this_divider. 398 399config SYS_FSL_DUART_CLK_DIV 400 int "DUART clock divider" 401 default 1 if ARCH_LS1043A 402 default 2 403 help 404 This is the divider that is used to derive DUART clock from Platform 405 clock, in another word DUART_clk = Platform_clk / this_divider. 406 407config SYS_FSL_I2C_CLK_DIV 408 int "I2C clock divider" 409 default 1 if ARCH_LS1043A 410 default 2 411 help 412 This is the divider that is used to derive I2C clock from Platform 413 clock, in another word I2C_clk = Platform_clk / this_divider. 414 415config SYS_FSL_IFC_CLK_DIV 416 int "IFC clock divider" 417 default 1 if ARCH_LS1043A 418 default 2 419 help 420 This is the divider that is used to derive IFC clock from Platform 421 clock, in another word IFC_clk = Platform_clk / this_divider. 422 423config SYS_FSL_LPUART_CLK_DIV 424 int "LPUART clock divider" 425 default 1 if ARCH_LS1043A 426 default 2 427 help 428 This is the divider that is used to derive LPUART clock from Platform 429 clock, in another word LPUART_clk = Platform_clk / this_divider. 430 431config SYS_FSL_SDHC_CLK_DIV 432 int "SDHC clock divider" 433 default 1 if ARCH_LS1043A 434 default 1 if ARCH_LS1012A 435 default 2 436 help 437 This is the divider that is used to derive SDHC clock from Platform 438 clock, in another word SDHC_clk = Platform_clk / this_divider. 439endmenu 440 441config RESV_RAM 442 bool 443 help 444 Reserve memory from the top, tracked by gd->arch.resv_ram. This 445 reserved RAM can be used by special driver that resides in memory 446 after U-Boot exits. It's up to implementation to allocate and allow 447 access to this reserved memory. For example, the reserved RAM can 448 be at the high end of physical memory. The reserve RAM may be 449 excluded from memory bank(s) passed to OS, or marked as reserved. 450 451config SYS_FSL_EC1 452 bool 453 help 454 Ethernet controller 1, this is connected to MAC3. 455 Provides DPAA2 capabilities 456 457config SYS_FSL_EC2 458 bool 459 help 460 Ethernet controller 2, this is connected to MAC4. 461 Provides DPAA2 capabilities 462 463config SYS_FSL_ERRATUM_A008336 464 bool 465 466config SYS_FSL_ERRATUM_A008514 467 bool 468 469config SYS_FSL_ERRATUM_A008585 470 bool 471 472config SYS_FSL_ERRATUM_A008850 473 bool 474 475config SYS_FSL_ERRATUM_A009203 476 bool 477 478config SYS_FSL_ERRATUM_A009635 479 bool 480 481config SYS_FSL_ERRATUM_A009660 482 bool 483 484config SYS_FSL_ERRATUM_A009929 485 bool 486 487 488config SYS_FSL_HAS_RGMII 489 bool 490 depends on SYS_FSL_EC1 || SYS_FSL_EC2 491 492 493config SYS_MC_RSV_MEM_ALIGN 494 hex "Management Complex reserved memory alignment" 495 depends on RESV_RAM 496 default 0x20000000 if ARCH_LS2080A 497 default 0x70000000 if ARCH_LS1088A 498 help 499 Reserved memory needs to be aligned for MC to use. Default value 500 is 512MB. 501 502config SPL_LDSCRIPT 503 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 504 505config HAS_FSL_XHCI_USB 506 bool 507 default y if ARCH_LS1043A || ARCH_LS1046A 508 help 509 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 510 pins, select it when the pins are assigned to USB. 511