1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 10config ARCH_LS1043A 11 bool 12 select ARMV8_SET_SMPEN 13 select FSL_LSCH2 14 select SYS_FSL_DDR 15 select SYS_FSL_DDR_BE 16 select SYS_FSL_DDR_VER_50 17 select SYS_FSL_ERRATUM_A008850 18 select SYS_FSL_ERRATUM_A009660 19 select SYS_FSL_ERRATUM_A009663 20 select SYS_FSL_ERRATUM_A009929 21 select SYS_FSL_ERRATUM_A009942 22 select SYS_FSL_ERRATUM_A010315 23 select SYS_FSL_ERRATUM_A010539 24 select SYS_FSL_HAS_DDR3 25 select SYS_FSL_HAS_DDR4 26 select ARCH_EARLY_INIT_R 27 28config ARCH_LS1046A 29 bool 30 select ARMV8_SET_SMPEN 31 select FSL_LSCH2 32 select SYS_FSL_DDR 33 select SYS_FSL_DDR_BE 34 select SYS_FSL_DDR_VER_50 35 select SYS_FSL_ERRATUM_A008511 36 select SYS_FSL_ERRATUM_A009801 37 select SYS_FSL_ERRATUM_A009803 38 select SYS_FSL_ERRATUM_A009942 39 select SYS_FSL_ERRATUM_A010165 40 select SYS_FSL_ERRATUM_A010539 41 select SYS_FSL_HAS_DDR4 42 select SYS_FSL_SRDS_2 43 select ARCH_EARLY_INIT_R 44 45config ARCH_LS2080A 46 bool 47 select ARMV8_SET_SMPEN 48 select FSL_LSCH3 49 select SYS_FSL_DDR 50 select SYS_FSL_DDR_LE 51 select SYS_FSL_DDR_VER_50 52 select SYS_FSL_HAS_DP_DDR 53 select SYS_FSL_HAS_SEC 54 select SYS_FSL_HAS_DDR4 55 select SYS_FSL_SEC_COMPAT_5 56 select SYS_FSL_SEC_LE 57 select SYS_FSL_SRDS_2 58 select SYS_FSL_ERRATUM_A008336 59 select SYS_FSL_ERRATUM_A008511 60 select SYS_FSL_ERRATUM_A008514 61 select SYS_FSL_ERRATUM_A008585 62 select SYS_FSL_ERRATUM_A009635 63 select SYS_FSL_ERRATUM_A009663 64 select SYS_FSL_ERRATUM_A009801 65 select SYS_FSL_ERRATUM_A009803 66 select SYS_FSL_ERRATUM_A009942 67 select SYS_FSL_ERRATUM_A010165 68 select ARCH_EARLY_INIT_R 69 70config FSL_LSCH2 71 bool 72 select SYS_FSL_HAS_SEC 73 select SYS_FSL_SEC_COMPAT_5 74 select SYS_FSL_SEC_BE 75 select SYS_FSL_SRDS_1 76 select SYS_HAS_SERDES 77 78config FSL_LSCH3 79 bool 80 select SYS_FSL_SRDS_1 81 select SYS_HAS_SERDES 82 83menu "Layerscape architecture" 84 depends on FSL_LSCH2 || FSL_LSCH3 85 86config FSL_PCIE_COMPAT 87 string "PCIe compatible of Kernel DT" 88 depends on PCIE_LAYERSCAPE 89 default "fsl,ls1012a-pcie" if ARCH_LS1012A 90 default "fsl,ls1043a-pcie" if ARCH_LS1043A 91 default "fsl,ls1046a-pcie" if ARCH_LS1046A 92 default "fsl,ls2080a-pcie" if ARCH_LS2080A 93 help 94 This compatible is used to find pci controller node in Kernel DT 95 to complete fixup. 96 97config HAS_FEATURE_GIC64K_ALIGN 98 bool 99 default y if ARCH_LS1043A 100 101config HAS_FEATURE_ENHANCED_MSI 102 bool 103 default y if ARCH_LS1043A 104 105menu "Layerscape PPA" 106config FSL_LS_PPA 107 bool "FSL Layerscape PPA firmware support" 108 depends on !ARMV8_PSCI 109 select ARMV8_SEC_FIRMWARE_SUPPORT 110 select SEC_FIRMWARE_ARMV8_PSCI 111 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 112 help 113 The FSL Primary Protected Application (PPA) is a software component 114 which is loaded during boot stage, and then remains resident in RAM 115 and runs in the TrustZone after boot. 116 Say y to enable it. 117choice 118 prompt "FSL Layerscape PPA firmware loading-media select" 119 depends on FSL_LS_PPA 120 default SYS_LS_PPA_FW_IN_XIP 121 122config SYS_LS_PPA_FW_IN_XIP 123 bool "XIP" 124 help 125 Say Y here if the PPA firmware locate at XIP flash, such 126 as NOR or QSPI flash. 127 128endchoice 129 130config SYS_LS_PPA_FW_ADDR 131 hex "Address of PPA firmware loading from" 132 depends on FSL_LS_PPA 133 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 134 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 135 help 136 If the PPA firmware locate at XIP flash, such as NOR or 137 QSPI flash, this address is a directly memory-mapped. 138 If it is in a serial accessed flash, such as NAND and SD 139 card, it is a byte offset. 140endmenu 141 142config SYS_FSL_ERRATUM_A010315 143 bool "Workaround for PCIe erratum A010315" 144 145config SYS_FSL_ERRATUM_A010539 146 bool "Workaround for PIN MUX erratum A010539" 147 148config MAX_CPUS 149 int "Maximum number of CPUs permitted for Layerscape" 150 default 4 if ARCH_LS1043A 151 default 4 if ARCH_LS1046A 152 default 16 if ARCH_LS2080A 153 default 1 154 help 155 Set this number to the maximum number of possible CPUs in the SoC. 156 SoCs may have multiple clusters with each cluster may have multiple 157 ports. If some ports are reserved but higher ports are used for 158 cores, count the reserved ports. This will allocate enough memory 159 in spin table to properly handle all cores. 160 161config SECURE_BOOT 162 bool "Secure Boot" 163 help 164 Enable Freescale Secure Boot feature 165 166config QSPI_AHB_INIT 167 bool "Init the QSPI AHB bus" 168 help 169 The default setting for QSPI AHB bus just support 3bytes addressing. 170 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 171 bus for those flashes to support the full QSPI flash size. 172 173config SYS_FSL_IFC_BANK_COUNT 174 int "Maximum banks of Integrated flash controller" 175 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 176 default 4 if ARCH_LS1043A 177 default 4 if ARCH_LS1046A 178 default 8 if ARCH_LS2080A 179 180config SYS_FSL_HAS_DP_DDR 181 bool 182 183config SYS_FSL_SRDS_1 184 bool 185 186config SYS_FSL_SRDS_2 187 bool 188 189config SYS_HAS_SERDES 190 bool 191 192endmenu 193 194menu "Layerscape clock tree configuration" 195 depends on FSL_LSCH2 || FSL_LSCH3 196 197config SYS_FSL_CLK 198 bool "Enable clock tree initialization" 199 default y 200 201config CLUSTER_CLK_FREQ 202 int "Reference clock of core cluster" 203 depends on ARCH_LS1012A 204 default 100000000 205 help 206 This number is the reference clock frequency of core PLL. 207 For most platforms, the core PLL and Platform PLL have the same 208 reference clock, but for some platforms, LS1012A for instance, 209 they are provided sepatately. 210 211config SYS_FSL_PCLK_DIV 212 int "Platform clock divider" 213 default 1 if ARCH_LS1043A 214 default 1 if ARCH_LS1046A 215 default 2 216 help 217 This is the divider that is used to derive Platform clock from 218 Platform PLL, in another word: 219 Platform_clk = Platform_PLL_freq / this_divider 220 221config SYS_FSL_DSPI_CLK_DIV 222 int "DSPI clock divider" 223 default 1 if ARCH_LS1043A 224 default 2 225 help 226 This is the divider that is used to derive DSPI clock from Platform 227 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 228 229config SYS_FSL_DUART_CLK_DIV 230 int "DUART clock divider" 231 default 1 if ARCH_LS1043A 232 default 2 233 help 234 This is the divider that is used to derive DUART clock from Platform 235 clock, in another word DUART_clk = Platform_clk / this_divider. 236 237config SYS_FSL_I2C_CLK_DIV 238 int "I2C clock divider" 239 default 1 if ARCH_LS1043A 240 default 2 241 help 242 This is the divider that is used to derive I2C clock from Platform 243 clock, in another word I2C_clk = Platform_clk / this_divider. 244 245config SYS_FSL_IFC_CLK_DIV 246 int "IFC clock divider" 247 default 1 if ARCH_LS1043A 248 default 2 249 help 250 This is the divider that is used to derive IFC clock from Platform 251 clock, in another word IFC_clk = Platform_clk / this_divider. 252 253config SYS_FSL_LPUART_CLK_DIV 254 int "LPUART clock divider" 255 default 1 if ARCH_LS1043A 256 default 2 257 help 258 This is the divider that is used to derive LPUART clock from Platform 259 clock, in another word LPUART_clk = Platform_clk / this_divider. 260 261config SYS_FSL_SDHC_CLK_DIV 262 int "SDHC clock divider" 263 default 1 if ARCH_LS1043A 264 default 1 if ARCH_LS1012A 265 default 2 266 help 267 This is the divider that is used to derive SDHC clock from Platform 268 clock, in another word SDHC_clk = Platform_clk / this_divider. 269endmenu 270 271config SYS_FSL_ERRATUM_A008336 272 bool 273 274config SYS_FSL_ERRATUM_A008514 275 bool 276 277config SYS_FSL_ERRATUM_A008585 278 bool 279 280config SYS_FSL_ERRATUM_A008850 281 bool 282 283config SYS_FSL_ERRATUM_A009635 284 bool 285 286config SYS_FSL_ERRATUM_A009660 287 bool 288 289config SYS_FSL_ERRATUM_A009929 290 bool 291