1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A008997 20 select SYS_FSL_ERRATUM_A009008 21 select SYS_FSL_ERRATUM_A009660 22 select SYS_FSL_ERRATUM_A009663 23 select SYS_FSL_ERRATUM_A009798 24 select SYS_FSL_ERRATUM_A009929 25 select SYS_FSL_ERRATUM_A009942 26 select SYS_FSL_ERRATUM_A010315 27 select SYS_FSL_ERRATUM_A010539 28 select SYS_FSL_HAS_DDR3 29 select SYS_FSL_HAS_DDR4 30 select ARCH_EARLY_INIT_R 31 select BOARD_EARLY_INIT_F 32 imply SCSI 33 imply CMD_PCI 34 35config ARCH_LS1046A 36 bool 37 select ARMV8_SET_SMPEN 38 select FSL_LSCH2 39 select SYS_FSL_DDR 40 select SYS_FSL_DDR_BE 41 select SYS_FSL_DDR_VER_50 42 select SYS_FSL_ERRATUM_A008336 43 select SYS_FSL_ERRATUM_A008511 44 select SYS_FSL_ERRATUM_A008850 45 select SYS_FSL_ERRATUM_A008997 46 select SYS_FSL_ERRATUM_A009008 47 select SYS_FSL_ERRATUM_A009798 48 select SYS_FSL_ERRATUM_A009801 49 select SYS_FSL_ERRATUM_A009803 50 select SYS_FSL_ERRATUM_A009942 51 select SYS_FSL_ERRATUM_A010165 52 select SYS_FSL_ERRATUM_A010539 53 select SYS_FSL_HAS_DDR4 54 select SYS_FSL_SRDS_2 55 select ARCH_EARLY_INIT_R 56 select BOARD_EARLY_INIT_F 57 imply SCSI 58 59config ARCH_LS1088A 60 bool 61 select ARMV8_SET_SMPEN 62 select FSL_LSCH3 63 select SYS_FSL_DDR 64 select SYS_FSL_DDR_LE 65 select SYS_FSL_DDR_VER_50 66 select SYS_FSL_EC1 67 select SYS_FSL_EC2 68 select SYS_FSL_ERRATUM_A009803 69 select SYS_FSL_ERRATUM_A009942 70 select SYS_FSL_ERRATUM_A010165 71 select SYS_FSL_ERRATUM_A008511 72 select SYS_FSL_ERRATUM_A008850 73 select SYS_FSL_HAS_CCI400 74 select SYS_FSL_HAS_DDR4 75 select SYS_FSL_HAS_RGMII 76 select SYS_FSL_HAS_SEC 77 select SYS_FSL_SEC_COMPAT_5 78 select SYS_FSL_SEC_LE 79 select SYS_FSL_SRDS_1 80 select SYS_FSL_SRDS_2 81 select FSL_TZASC_1 82 select ARCH_EARLY_INIT_R 83 select BOARD_EARLY_INIT_F 84 85config ARCH_LS2080A 86 bool 87 select ARMV8_SET_SMPEN 88 select ARM_ERRATA_826974 89 select ARM_ERRATA_828024 90 select ARM_ERRATA_829520 91 select ARM_ERRATA_833471 92 select FSL_LSCH3 93 select SYS_FSL_DDR 94 select SYS_FSL_DDR_LE 95 select SYS_FSL_DDR_VER_50 96 select SYS_FSL_HAS_CCN504 97 select SYS_FSL_HAS_DP_DDR 98 select SYS_FSL_HAS_SEC 99 select SYS_FSL_HAS_DDR4 100 select SYS_FSL_SEC_COMPAT_5 101 select SYS_FSL_SEC_LE 102 select SYS_FSL_SRDS_2 103 select FSL_TZASC_1 104 select FSL_TZASC_2 105 select SYS_FSL_ERRATUM_A008336 106 select SYS_FSL_ERRATUM_A008511 107 select SYS_FSL_ERRATUM_A008514 108 select SYS_FSL_ERRATUM_A008585 109 select SYS_FSL_ERRATUM_A008997 110 select SYS_FSL_ERRATUM_A009008 111 select SYS_FSL_ERRATUM_A009635 112 select SYS_FSL_ERRATUM_A009663 113 select SYS_FSL_ERRATUM_A009798 114 select SYS_FSL_ERRATUM_A009801 115 select SYS_FSL_ERRATUM_A009803 116 select SYS_FSL_ERRATUM_A009942 117 select SYS_FSL_ERRATUM_A010165 118 select SYS_FSL_ERRATUM_A009203 119 select ARCH_EARLY_INIT_R 120 select BOARD_EARLY_INIT_F 121 122config FSL_LSCH2 123 bool 124 select SYS_FSL_HAS_CCI400 125 select SYS_FSL_HAS_SEC 126 select SYS_FSL_SEC_COMPAT_5 127 select SYS_FSL_SEC_BE 128 select SYS_FSL_SRDS_1 129 select SYS_HAS_SERDES 130 131config FSL_LSCH3 132 bool 133 select SYS_FSL_SRDS_1 134 select SYS_HAS_SERDES 135 136config FSL_MC_ENET 137 bool "Management Complex network" 138 depends on ARCH_LS2080A || ARCH_LS1088A 139 default y 140 select RESV_RAM 141 help 142 Enable Management Complex (MC) network 143 144menu "Layerscape architecture" 145 depends on FSL_LSCH2 || FSL_LSCH3 146 147config FSL_PCIE_COMPAT 148 string "PCIe compatible of Kernel DT" 149 depends on PCIE_LAYERSCAPE 150 default "fsl,ls1012a-pcie" if ARCH_LS1012A 151 default "fsl,ls1043a-pcie" if ARCH_LS1043A 152 default "fsl,ls1046a-pcie" if ARCH_LS1046A 153 default "fsl,ls2080a-pcie" if ARCH_LS2080A 154 default "fsl,ls1088a-pcie" if ARCH_LS1088A 155 help 156 This compatible is used to find pci controller node in Kernel DT 157 to complete fixup. 158 159config HAS_FEATURE_GIC64K_ALIGN 160 bool 161 default y if ARCH_LS1043A 162 163config HAS_FEATURE_ENHANCED_MSI 164 bool 165 default y if ARCH_LS1043A 166 167menu "Layerscape PPA" 168config FSL_LS_PPA 169 bool "FSL Layerscape PPA firmware support" 170 depends on !ARMV8_PSCI 171 select ARMV8_SEC_FIRMWARE_SUPPORT 172 select SEC_FIRMWARE_ARMV8_PSCI 173 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 174 help 175 The FSL Primary Protected Application (PPA) is a software component 176 which is loaded during boot stage, and then remains resident in RAM 177 and runs in the TrustZone after boot. 178 Say y to enable it. 179 180config SPL_FSL_LS_PPA 181 bool "FSL Layerscape PPA firmware support for SPL build" 182 depends on !ARMV8_PSCI 183 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 184 select SEC_FIRMWARE_ARMV8_PSCI 185 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 186 help 187 The FSL Primary Protected Application (PPA) is a software component 188 which is loaded during boot stage, and then remains resident in RAM 189 and runs in the TrustZone after boot. This is to load PPA during SPL 190 stage instead of the RAM version of U-Boot. Once PPA is initialized, 191 the rest of U-Boot (including RAM version) runs at EL2. 192choice 193 prompt "FSL Layerscape PPA firmware loading-media select" 194 depends on FSL_LS_PPA 195 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 196 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 197 default SYS_LS_PPA_FW_IN_XIP 198 199config SYS_LS_PPA_FW_IN_XIP 200 bool "XIP" 201 help 202 Say Y here if the PPA firmware locate at XIP flash, such 203 as NOR or QSPI flash. 204 205config SYS_LS_PPA_FW_IN_MMC 206 bool "eMMC or SD Card" 207 help 208 Say Y here if the PPA firmware locate at eMMC/SD card. 209 210config SYS_LS_PPA_FW_IN_NAND 211 bool "NAND" 212 help 213 Say Y here if the PPA firmware locate at NAND flash. 214 215endchoice 216 217config SYS_LS_PPA_FW_ADDR 218 hex "Address of PPA firmware loading from" 219 depends on FSL_LS_PPA 220 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 221 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 222 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 223 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 224 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 225 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 226 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 227 228 help 229 If the PPA firmware locate at XIP flash, such as NOR or 230 QSPI flash, this address is a directly memory-mapped. 231 If it is in a serial accessed flash, such as NAND and SD 232 card, it is a byte offset. 233 234config SYS_LS_PPA_ESBC_ADDR 235 hex "hdr address of PPA firmware loading from" 236 depends on FSL_LS_PPA && CHAIN_OF_TRUST 237 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 238 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 239 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 240 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 241 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 242 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 243 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 244 help 245 If the PPA header firmware locate at XIP flash, such as NOR or 246 QSPI flash, this address is a directly memory-mapped. 247 If it is in a serial accessed flash, such as NAND and SD 248 card, it is a byte offset. 249 250config LS_PPA_ESBC_HDR_SIZE 251 hex "Length of PPA ESBC header" 252 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 253 default 0x2000 254 help 255 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 256 NAND to memory to validate PPA image. 257 258endmenu 259 260config SYS_FSL_ERRATUM_A008997 261 bool "Workaround for USB PHY erratum A008997" 262 263config SYS_FSL_ERRATUM_A009008 264 bool "Workaround for USB PHY erratum A009008" 265 266config SYS_FSL_ERRATUM_A009798 267 bool "Workaround for USB PHY erratum A009798" 268 269config SYS_FSL_ERRATUM_A010315 270 bool "Workaround for PCIe erratum A010315" 271 272config SYS_FSL_ERRATUM_A010539 273 bool "Workaround for PIN MUX erratum A010539" 274 275config MAX_CPUS 276 int "Maximum number of CPUs permitted for Layerscape" 277 default 4 if ARCH_LS1043A 278 default 4 if ARCH_LS1046A 279 default 16 if ARCH_LS2080A 280 default 8 if ARCH_LS1088A 281 default 1 282 help 283 Set this number to the maximum number of possible CPUs in the SoC. 284 SoCs may have multiple clusters with each cluster may have multiple 285 ports. If some ports are reserved but higher ports are used for 286 cores, count the reserved ports. This will allocate enough memory 287 in spin table to properly handle all cores. 288 289config SECURE_BOOT 290 bool "Secure Boot" 291 help 292 Enable Freescale Secure Boot feature 293 294config QSPI_AHB_INIT 295 bool "Init the QSPI AHB bus" 296 help 297 The default setting for QSPI AHB bus just support 3bytes addressing. 298 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 299 bus for those flashes to support the full QSPI flash size. 300 301config SYS_CCI400_OFFSET 302 hex "Offset for CCI400 base" 303 depends on SYS_FSL_HAS_CCI400 304 default 0x3090000 if ARCH_LS1088A 305 default 0x180000 if FSL_LSCH2 306 help 307 Offset for CCI400 base 308 CCI400 base addr = CCSRBAR + CCI400_OFFSET 309 310config SYS_FSL_IFC_BANK_COUNT 311 int "Maximum banks of Integrated flash controller" 312 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 313 default 4 if ARCH_LS1043A 314 default 4 if ARCH_LS1046A 315 default 8 if ARCH_LS2080A || ARCH_LS1088A 316 317config SYS_FSL_HAS_CCI400 318 bool 319 320config SYS_FSL_HAS_CCN504 321 bool 322 323config SYS_FSL_HAS_DP_DDR 324 bool 325 326config SYS_FSL_SRDS_1 327 bool 328 329config SYS_FSL_SRDS_2 330 bool 331 332config SYS_HAS_SERDES 333 bool 334 335config FSL_TZASC_1 336 bool 337 338config FSL_TZASC_2 339 bool 340 341endmenu 342 343menu "Layerscape clock tree configuration" 344 depends on FSL_LSCH2 || FSL_LSCH3 345 346config SYS_FSL_CLK 347 bool "Enable clock tree initialization" 348 default y 349 350config CLUSTER_CLK_FREQ 351 int "Reference clock of core cluster" 352 depends on ARCH_LS1012A 353 default 100000000 354 help 355 This number is the reference clock frequency of core PLL. 356 For most platforms, the core PLL and Platform PLL have the same 357 reference clock, but for some platforms, LS1012A for instance, 358 they are provided sepatately. 359 360config SYS_FSL_PCLK_DIV 361 int "Platform clock divider" 362 default 1 if ARCH_LS1043A 363 default 1 if ARCH_LS1046A 364 default 1 if ARCH_LS1088A 365 default 2 366 help 367 This is the divider that is used to derive Platform clock from 368 Platform PLL, in another word: 369 Platform_clk = Platform_PLL_freq / this_divider 370 371config SYS_FSL_DSPI_CLK_DIV 372 int "DSPI clock divider" 373 default 1 if ARCH_LS1043A 374 default 2 375 help 376 This is the divider that is used to derive DSPI clock from Platform 377 clock, in another word DSPI_clk = Platform_clk / this_divider. 378 379config SYS_FSL_DUART_CLK_DIV 380 int "DUART clock divider" 381 default 1 if ARCH_LS1043A 382 default 2 383 help 384 This is the divider that is used to derive DUART clock from Platform 385 clock, in another word DUART_clk = Platform_clk / this_divider. 386 387config SYS_FSL_I2C_CLK_DIV 388 int "I2C clock divider" 389 default 1 if ARCH_LS1043A 390 default 2 391 help 392 This is the divider that is used to derive I2C clock from Platform 393 clock, in another word I2C_clk = Platform_clk / this_divider. 394 395config SYS_FSL_IFC_CLK_DIV 396 int "IFC clock divider" 397 default 1 if ARCH_LS1043A 398 default 2 399 help 400 This is the divider that is used to derive IFC clock from Platform 401 clock, in another word IFC_clk = Platform_clk / this_divider. 402 403config SYS_FSL_LPUART_CLK_DIV 404 int "LPUART clock divider" 405 default 1 if ARCH_LS1043A 406 default 2 407 help 408 This is the divider that is used to derive LPUART clock from Platform 409 clock, in another word LPUART_clk = Platform_clk / this_divider. 410 411config SYS_FSL_SDHC_CLK_DIV 412 int "SDHC clock divider" 413 default 1 if ARCH_LS1043A 414 default 1 if ARCH_LS1012A 415 default 2 416 help 417 This is the divider that is used to derive SDHC clock from Platform 418 clock, in another word SDHC_clk = Platform_clk / this_divider. 419endmenu 420 421config RESV_RAM 422 bool 423 help 424 Reserve memory from the top, tracked by gd->arch.resv_ram. This 425 reserved RAM can be used by special driver that resides in memory 426 after U-Boot exits. It's up to implementation to allocate and allow 427 access to this reserved memory. For example, the reserved RAM can 428 be at the high end of physical memory. The reserve RAM may be 429 excluded from memory bank(s) passed to OS, or marked as reserved. 430 431config SYS_FSL_EC1 432 bool 433 help 434 Ethernet controller 1, this is connected to MAC3. 435 Provides DPAA2 capabilities 436 437config SYS_FSL_EC2 438 bool 439 help 440 Ethernet controller 2, this is connected to MAC4. 441 Provides DPAA2 capabilities 442 443config SYS_FSL_ERRATUM_A008336 444 bool 445 446config SYS_FSL_ERRATUM_A008514 447 bool 448 449config SYS_FSL_ERRATUM_A008585 450 bool 451 452config SYS_FSL_ERRATUM_A008850 453 bool 454 455config SYS_FSL_ERRATUM_A009203 456 bool 457 458config SYS_FSL_ERRATUM_A009635 459 bool 460 461config SYS_FSL_ERRATUM_A009660 462 bool 463 464config SYS_FSL_ERRATUM_A009929 465 bool 466 467 468config SYS_FSL_HAS_RGMII 469 bool 470 depends on SYS_FSL_EC1 || SYS_FSL_EC2 471 472 473config SYS_MC_RSV_MEM_ALIGN 474 hex "Management Complex reserved memory alignment" 475 depends on RESV_RAM 476 default 0x20000000 if ARCH_LS2080A 477 default 0x70000000 if ARCH_LS1088A 478 help 479 Reserved memory needs to be aligned for MC to use. Default value 480 is 512MB. 481 482config SPL_LDSCRIPT 483 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 484