1config ARCH_LS1012A
2	bool
3	select ARMV8_SET_SMPEN
4	select FSL_LSCH2
5	select SYS_FSL_DDR_BE
6	select SYS_FSL_MMDC
7	select SYS_FSL_ERRATUM_A010315
8
9config ARCH_LS1043A
10	bool
11	select ARMV8_SET_SMPEN
12	select FSL_LSCH2
13	select SYS_FSL_DDR
14	select SYS_FSL_DDR_BE
15	select SYS_FSL_DDR_VER_50
16	select SYS_FSL_ERRATUM_A008850
17	select SYS_FSL_ERRATUM_A009660
18	select SYS_FSL_ERRATUM_A009663
19	select SYS_FSL_ERRATUM_A009929
20	select SYS_FSL_ERRATUM_A009942
21	select SYS_FSL_ERRATUM_A010315
22	select SYS_FSL_ERRATUM_A010539
23	select SYS_FSL_HAS_DDR3
24	select SYS_FSL_HAS_DDR4
25
26config ARCH_LS1046A
27	bool
28	select ARMV8_SET_SMPEN
29	select FSL_LSCH2
30	select SYS_FSL_DDR
31	select SYS_FSL_DDR_BE
32	select SYS_FSL_DDR_VER_50
33	select SYS_FSL_ERRATUM_A008511
34	select SYS_FSL_ERRATUM_A009801
35	select SYS_FSL_ERRATUM_A009803
36	select SYS_FSL_ERRATUM_A009942
37	select SYS_FSL_ERRATUM_A010165
38	select SYS_FSL_ERRATUM_A010539
39	select SYS_FSL_HAS_DDR4
40	select SYS_FSL_SRDS_2
41
42config ARCH_LS2080A
43	bool
44	select ARMV8_SET_SMPEN
45	select FSL_LSCH3
46	select SYS_FSL_DDR
47	select SYS_FSL_DDR_LE
48	select SYS_FSL_DDR_VER_50
49	select SYS_FSL_HAS_DP_DDR
50	select SYS_FSL_HAS_SEC
51	select SYS_FSL_HAS_DDR4
52	select SYS_FSL_SEC_COMPAT_5
53	select SYS_FSL_SEC_LE
54	select SYS_FSL_SRDS_2
55	select SYS_FSL_ERRATUM_A008336
56	select SYS_FSL_ERRATUM_A008511
57	select SYS_FSL_ERRATUM_A008514
58	select SYS_FSL_ERRATUM_A008585
59	select SYS_FSL_ERRATUM_A009635
60	select SYS_FSL_ERRATUM_A009663
61	select SYS_FSL_ERRATUM_A009801
62	select SYS_FSL_ERRATUM_A009803
63	select SYS_FSL_ERRATUM_A009942
64	select SYS_FSL_ERRATUM_A010165
65
66config FSL_LSCH2
67	bool
68	select SYS_FSL_HAS_SEC
69	select SYS_FSL_SEC_COMPAT_5
70	select SYS_FSL_SEC_BE
71	select SYS_FSL_SRDS_1
72	select SYS_HAS_SERDES
73
74config FSL_LSCH3
75	bool
76	select SYS_FSL_SRDS_1
77	select SYS_HAS_SERDES
78
79menu "Layerscape architecture"
80	depends on FSL_LSCH2 || FSL_LSCH3
81
82config FSL_PCIE_COMPAT
83	string "PCIe compatible of Kernel DT"
84	depends on PCIE_LAYERSCAPE
85	default "fsl,ls1012a-pcie" if ARCH_LS1012A
86	default "fsl,ls1043a-pcie" if ARCH_LS1043A
87	default "fsl,ls1046a-pcie" if ARCH_LS1046A
88	default "fsl,ls2080a-pcie" if ARCH_LS2080A
89	help
90	  This compatible is used to find pci controller node in Kernel DT
91	  to complete fixup.
92
93menu "Layerscape PPA"
94config FSL_LS_PPA
95	bool "FSL Layerscape PPA firmware support"
96	depends on !ARMV8_PSCI
97	depends on ARCH_LS1043A || ARCH_LS1046A
98	select FSL_PPA_ARMV8_PSCI
99	help
100	  The FSL Primary Protected Application (PPA) is a software component
101	  which is loaded during boot stage, and then remains resident in RAM
102	  and runs in the TrustZone after boot.
103	  Say y to enable it.
104
105config FSL_PPA_ARMV8_PSCI
106	bool "PSCI implementation in PPA firmware"
107	depends on FSL_LS_PPA
108	help
109	  This config enables the ARMv8 PSCI implementation in PPA firmware.
110	  This is a private PSCI implementation and different from those
111	  implemented under the common ARMv8 PSCI framework.
112endmenu
113
114config SYS_FSL_ERRATUM_A010315
115	bool "Workaround for PCIe erratum A010315"
116
117config SYS_FSL_ERRATUM_A010539
118	bool "Workaround for PIN MUX erratum A010539"
119
120config MAX_CPUS
121	int "Maximum number of CPUs permitted for Layerscape"
122	default 4 if ARCH_LS1043A
123	default 4 if ARCH_LS1046A
124	default 16 if ARCH_LS2080A
125	default 1
126	help
127	  Set this number to the maximum number of possible CPUs in the SoC.
128	  SoCs may have multiple clusters with each cluster may have multiple
129	  ports. If some ports are reserved but higher ports are used for
130	  cores, count the reserved ports. This will allocate enough memory
131	  in spin table to properly handle all cores.
132
133config SECURE_BOOT
134	bool "Secure Boot"
135	help
136		Enable Freescale Secure Boot feature
137
138config QSPI_AHB_INIT
139	bool "Init the QSPI AHB bus"
140	help
141	  The default setting for QSPI AHB bus just support 3bytes addressing.
142	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
143	  bus for those flashes to support the full QSPI flash size.
144
145config SYS_FSL_IFC_BANK_COUNT
146	int "Maximum banks of Integrated flash controller"
147	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
148	default 4 if ARCH_LS1043A
149	default 4 if ARCH_LS1046A
150	default 8 if ARCH_LS2080A
151
152config SYS_FSL_HAS_DP_DDR
153	bool
154
155config SYS_FSL_SRDS_1
156	bool
157
158config SYS_FSL_SRDS_2
159	bool
160
161config SYS_HAS_SERDES
162	bool
163
164endmenu
165
166menu "Layerscape clock tree configuration"
167	depends on FSL_LSCH2 || FSL_LSCH3
168
169config SYS_FSL_CLK
170	bool "Enable clock tree initialization"
171	default y
172
173config CLUSTER_CLK_FREQ
174	int "Reference clock of core cluster"
175	depends on ARCH_LS1012A
176	default 100000000
177	help
178	  This number is the reference clock frequency of core PLL.
179	  For most platforms, the core PLL and Platform PLL have the same
180	  reference clock, but for some platforms, LS1012A for instance,
181	  they are provided sepatately.
182
183config SYS_FSL_PCLK_DIV
184	int "Platform clock divider"
185	default 1 if ARCH_LS1043A
186	default 1 if ARCH_LS1046A
187	default 2
188	help
189	  This is the divider that is used to derive Platform clock from
190	  Platform PLL, in another word:
191		Platform_clk = Platform_PLL_freq / this_divider
192
193config SYS_FSL_DSPI_CLK_DIV
194	int "DSPI clock divider"
195	default 1 if ARCH_LS1043A
196	default 2
197	help
198	  This is the divider that is used to derive DSPI clock from Platform
199	  PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
200
201config SYS_FSL_DUART_CLK_DIV
202	int "DUART clock divider"
203	default 1 if ARCH_LS1043A
204	default 2
205	help
206	  This is the divider that is used to derive DUART clock from Platform
207	  clock, in another word DUART_clk = Platform_clk / this_divider.
208
209config SYS_FSL_I2C_CLK_DIV
210	int "I2C clock divider"
211	default 1 if ARCH_LS1043A
212	default 2
213	help
214	  This is the divider that is used to derive I2C clock from Platform
215	  clock, in another word I2C_clk = Platform_clk / this_divider.
216
217config SYS_FSL_IFC_CLK_DIV
218	int "IFC clock divider"
219	default 1 if ARCH_LS1043A
220	default 2
221	help
222	  This is the divider that is used to derive IFC clock from Platform
223	  clock, in another word IFC_clk = Platform_clk / this_divider.
224
225config SYS_FSL_LPUART_CLK_DIV
226	int "LPUART clock divider"
227	default 1 if ARCH_LS1043A
228	default 2
229	help
230	  This is the divider that is used to derive LPUART clock from Platform
231	  clock, in another word LPUART_clk = Platform_clk / this_divider.
232
233config SYS_FSL_SDHC_CLK_DIV
234	int "SDHC clock divider"
235	default 1 if ARCH_LS1043A
236	default 1 if ARCH_LS1012A
237	default 2
238	help
239	  This is the divider that is used to derive SDHC clock from Platform
240	  clock, in another word SDHC_clk = Platform_clk / this_divider.
241endmenu
242
243config SYS_FSL_ERRATUM_A008336
244	bool
245
246config SYS_FSL_ERRATUM_A008514
247	bool
248
249config SYS_FSL_ERRATUM_A008585
250	bool
251
252config SYS_FSL_ERRATUM_A008850
253	bool
254
255config SYS_FSL_ERRATUM_A009635
256	bool
257
258config SYS_FSL_ERRATUM_A009660
259	bool
260
261config SYS_FSL_ERRATUM_A009929
262	bool
263